• 參數(shù)資料
    型號: ISP1161BD
    廠商: NXP SEMICONDUCTORS
    元件分類: 總線控制器
    英文描述: Full-speed Universal Serial Bus single-chip host and device controller
    中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
    封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
    文件頁數(shù): 19/127頁
    文件大小: 2762K
    代理商: ISP1161BD
    Philips Semiconductors
    ISP1161
    Full-speed USB single-chip host and device controller
    Product data
    Rev. 01 — 3 July 2001
    19 of 130
    9397 750 08313
    Philips Electronics N.V. 2001. All rights reserved.
    8.6 Interrupts
    ISP1161 has separate interrupt request pins for the USB HC (INT1) and the USB DC
    (INT2).
    8.6.1
    Pin configuration
    The interrupt output signals have four configuration modes:
    Level trigger, active LOW
    Level trigger, active HIGH
    Edge trigger, active LOW
    Edge trigger, active HIGH.
    Figure 20
    shows these four interrupt configuration modes. They are programmable
    through register settings, which are also used to disable or enable the signals.
    8.6.2
    HC’s interrupt output pin (INT1)
    To program the four configuration modes of the HC’s interrupt output signal (INT1),
    set bits 1 and 2 of the HcHardwareConfiguration register (20H - Read, A0H - Write).
    Bit 0 is used as the master enable setting for pin INT1.
    INT1 has many interrupt events. The relationship between pin INT1 and its interrupt
    events is shown as in
    Figure 21
    .
    Fig 20. Interrupt pin operating modes.
    MGT944
    INT active
    INT active
    clear or disable INT
    (2) INT is level triggered, active HIGH
    INT
    INT
    167 ns
    (3) INT is edge triggered, active LOW
    INT active
    INT
    167 ns
    (4) INT is edge triggered, active HIGH
    INT active
    clear or disable INT
    (1) INT is level triggered, active LOW
    INT
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