參數(shù)資料
型號： ISP1161BD
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 59/127頁
文件大小： 2762K
代理商： ISP1161BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
59 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
Code (Hex): 03 —
read
Code (Hex): 83 —
write
13.1.5
HcInterruptEnable Register
Each enable bit in the HcInterruptEnable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used
to control which events generate a hardware interrupt. When these three conditions
occur:
A bit is set in the HcInterruptStatus register
The corresponding bit in the HcInterruptEnable register is set
The MasterInterruptEnable bit is set
then a hardware interrupt is requested on the host bus.
Writing a logic1 to a bit in this register sets the corresponding bit, whereas writing a
logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the
current value of this register is returned.
Table 23: HcInterruptStatus Register: bit description
Bit
Symbol
Description
31 to 8
reserved
7
reserved
6
RHSC
RootHubStatusChange:
This bit is set when the content of
HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
5
FNO
FrameNumberOverflow:
This bit is set when the MSB of
HcFmNumber (bit 15) changes value, from logic 0 to 1 or from
logic 1 to 0.
4
UE
UnrecoverableError:
This bit is set when the HC detects a
system error not related to USB. The HC should not proceed with
any processing nor signaling before the system error has been
corrected. The HCD clears this bit after HC has been reset.
PHCI: Always set to logic 0.
3
RD
ResumeDetected:
This bit is set when the HC detects that a
device on the USB is asserting resume signaling. It is the transition
from no resume signaling to resume signaling causing this bit to be
set. This bit is not set when HCD sets the USBRESUME state.
2
SF
StartOfFrame:
At the start of each frame, this bit is set by the HC
and an SOF generated.
1
-
reserved
0
SO
SchedulingOverrun:
This bit is set when USB schedules for
current frame overruns. A scheduling overrun will also cause the
SchedulingOverrunCount of HcCommandStatus to be
incremented.
相關PDF資料
PDF描述
ISP1161BM Full-speed Universal Serial Bus single-chip host and device controller
ISP1181ABS INDUCTOR 1.0NH +-.3NH FIXED SMD
ISP1181A Full-speed Universal Serial Bus peripheral controller
ISP1181ADGG Full-speed Universal Serial Bus peripheral controller
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相關代理商/技術參數(shù)
參數(shù)描述
ISP1161BM 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller
ISP1181 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device
ISP1181A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS,518 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
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