參數(shù)資料
型號(hào)： ISP1161BD
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 93/127頁
文件大小： 2762K
代理商： ISP1161BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
93 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
14.1.5
Write/Read Interrupt Enable Register
This command is used to individually enable/disable interrupts from all endpoints, as
well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend,
resume, reset). A bus reset will not change any of the programmed bit values.
The command accesses the Interrupt Enable Register, which consists of 4 bytes. The
bit allocation is given in
Table 83
.
Code (Hex): C2/C3 —
write/read Interrupt Enable Register
Transaction —
write/read 2 words
Table 83: Interrupt Enable Register: bit allocation
Bit
31
Symbol
Reset
0
Access
R/W
Bit
23
Symbol
IEP14
Reset
0
Access
R/W
Bit
15
Symbol
IEP6
Reset
0
Access
R/W
Bit
7
Symbol
reserved
Reset
0
Access
R/W
30
29
28
27
26
25
24
reserved
0
0
0
0
0
0
0
R/W
22
IEP13
0
R/W
14
IEP5
0
R/W
6
reserved
0
R/W
R/W
21
IEP12
0
R/W
13
IEP4
0
R/W
5
IEPSOF
0
R/W
R/W
20
IEP11
0
R/W
12
IEP3
0
R/W
4
IESOF
0
R/W
R/W
19
IEP10
0
R/W
11
IEP2
0
R/W
3
IEEOT
0
R/W
R/W
18
IEP9
0
R/W
10
IEP1
0
R/W
2
IESUSP
0
R/W
R/W
17
IEP8
0
R/W
9
IEP0IN
0
R/W
1
IERESM
0
R/W
R/W
16
IEP7
0
R/W
8
IEP0OUT
0
R/W
0
IERST
0
R/W
Table 84: Interrupt Enable Register: bit description
Bit
Symbol
31 to 24
-
23 to 10
IEP14 to IEP1
9
IEP0IN
8
IEP0OUT
7, 6
-
5
IEPSOF
Description
reserved; must write logic 0
A logic 1 enables interrupts from the indicated endpoint.
A logic 1 enables interrupts from the control IN endpoint.
A logic 1 enables interrupts from the control OUT endpoint.
reserved
A logic 1 enables 1 ms interrupts upon detection of Pseudo
SOF.
A logic 1 enables interrupt upon SOF detection.
A logic 1 enables interrupt upon EOT detection.
A logic 1 enables interrupt upon detection of ‘suspend’ state.
A logic 1 enables interrupt upon detection of a ‘resume’ state.
A logic 1 enables interrupt upon detection of a bus reset.
4
3
2
1
0
IESOF
IEEOT
IESUSP
IERESM
IERST
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ISP1181ABS,518 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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