參數(shù)資料
型號(hào): ISP1362EE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁(yè)數(shù): 33/150頁(yè)
文件大?。?/td> 647K
代理商: ISP1362EE
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)當(dāng)前第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
33 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
communicates with the A-device as long as it wishes. When the B-device
fi
nishes
communicating with the A-device, both the devices
fi
nally go into the idle state. See
Figure 18
and
Figure 19
.
11.3 Session Request Protocol (SRP)
As a dual-role device, the ISP1362 can initiate and respond to SRP. The B-device
initiates SRP by data line pulsing followed by V
BUS
pulsing. The A-device can detect
either data line pulsing or V
BUS
pulsing.
11.3.1
B-device initiating SRP
The ISP1362 can initiate SRP by performing the following steps:
1. Detect initial conditions [read ID_REG, B_SESS_END and SE0_2MS (bits 0,
2 and 9) of the OtgStatus register].
2. Start data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 1].
3. Wait for 5 ms to 10 ms.
4. Stop data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 0].
5. Start V
BUS
pulsing [set CHRG_V
BUS
(bit 1) of the OtgControl register to logic 1].
6. Wait for 10 ms to 20 ms.
7. Stop V
BUS
pulsing [set CHRG_V
BUS
(bit 1) of the OtgControl register to logic 0].
8. Discharge V
BUS
for about 30 ms [by using DISCHRG_V
BUS
(bit 2) of the
OtgControl register], optional.
The B-device must complete both data line pulsing and V
BUS
pulsing within 100 ms.
11.3.2
A-device responding to SRP
The A-device must be able to respond to one of the two SRP events: data line pulsing
or V
BUS
pulsing. The ISP1362 allows you to choose which SRP to support and has a
mechanism to disable or enable the SRP detection. This is useful for some
applications under certain cases. For example, if the A-device battery is low, it may
not want to turn on its V
BUS
by detecting SRP. In this case, it may choose to disable
the SRP detection function.
When the data line SRP detection is used, the ISP1362 can detect either the
DP pulsing or the DM pulsing. This means a peripheral-only device can initiate data
line pulsing SRP through DP (full-speed) or DM (low-speed). A dual-role device will
always initiate data line pulsing SRP through DP because it is a full-speed device.
Steps to enable the SRP detection by V
BUS
pulsing:
Set A_SEL_SRP (bit 9) of the OtgControl register to logic 0.
Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.
Steps to enable the SRP detection by data line pulsing:
Set A_SEL_SRP (bit 9) of the OtgControl register to logic 1.
Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1.
Steps to disable the SRP detection:
Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 0.
相關(guān)PDF資料
PDF描述
ISP1501 Hi-Speed Universal Serial Bus peripheral transceiver
ISP1520 Hi-Speed Universal Serial Bus hub controller
ISP1520BD Hi-Speed Universal Serial Bus hub controller
ISP1521 Hi-Speed Universal Serial Bus hub controller
ISP1521BE Hi-Speed Universal Serial Bus hub controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1362EE,518 功能描述:USB 接口集成電路 USB OTG HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362EE,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362EE,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362EE/01 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip Universal Serial Bus On-The-Go controller
ISP1362EE-S 功能描述:IC USB CTRL SNGL CHIP 64TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN(6x6) 包裝:* 其它名稱:Q6396337A