參數(shù)資料
型號(hào): ISP1561BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù): 34/103頁(yè)
文件大?。?/td> 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
36 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.2 HcControl register (address: content of the base address register + 04h)
The HcControl register denes the operating modes for the Host Controller. All the elds
in this register, except HCFS and RWC, are modied only by the HCD. The bit allocation is
given in Table 45.
Table 44.
HcRevision register: bit description
Bit
Symbol
Description
31 to 9
-
reserved
8L
Legacy:
0 — Does not support legacy devices
1 — Supports legacy keyboard and mouse
7 to 0
REV[7:0]
Revision: This read-only eld contains the BCD representation of the
version of the HCI specication that is implemented by this Host
Controller. For example, a value of 11h corresponds to version 1.1. All
of the Host Controller implementations that are compliant with this
specication must have a value of 10h.
Table 45.
HcControl register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
RWE
RWC
IR
Reset
00000000
Access
-----
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
HCFS[1:0]
BLE
CLE
IE
PLE
CBSR[1:0]
Reset
00000000
Access
R/W
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