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ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
38 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.3 HcCommandStatus register (address: content of the base address
register + 08h)
The HcCommandStatus register is used by the Host Controller to receive commands
issued by the HCD. It also reects the current status of the Host Controller. To the HCD, it
appears as a “write to set” register. The Host Controller must ensure that bits written as
logic 1 become set in the register while bits written as logic 0 remain unchanged in the
register. The HCD may issue multiple distinct commands to the Host Controller without
concern for corrupting previously issued commands. The HCD has normal read access to
all bits.
The SOC[1:0] (Scheduling Overrun Count) eld indicates the number of frames with which
the Host Controller has detected the scheduling overrun error. This occurs when the
periodic list does not complete before EOF. When a scheduling overrun error is detected,
the Host Controller increments the counter and sets the SO (Scheduling Overrun) eld in
the HcInterruptStatus register.
Table 47 shows the bit allocation of the HcCommandStatus
register.
4
CLE
Control List Enable: This bit is set to enable the processing of the
control list in the next frame. If cleared by the HCD, processing of the
control list does not occur after the next SOF. The Host Controller must
check this bit whenever it wants to process the list. When disabled, the
HCD may modify the list. If HcControlCurrentED is pointing to an ED to
be removed, the HCD must advance the pointer by updating
HcControlCurrentED before re-enabling processing of the list.
3IE
Isochronous Enable: This bit is used by the HCD to enable or disable
processing of isochronous EDs. While processing the periodic list in a
frame, the Host Controller checks the status of this bit when it nds an
isochronous ED (that is, the Format bit of ED is logic 1; for details, refer
(enabled), the Host Controller continues processing EDs. If cleared
(disabled), the Host Controller halts processing of the periodic list, which
now contains only isochronous EDs, and begins processing the bulk or
control lists. Setting this bit is guaranteed to take effect in the next frame
and not the current frame.
2
PLE
Periodic List Enable: This bit is set to enable the processing of the
periodic list in the next frame. If cleared by the HCD, processing of the
periodic list does not occur after the next SOF. The Host Controller must
check this bit before it starts processing the list.
1 to 0
CBSR[1:0]
Control Bulk Service Ratio: This species the service ratio of control
EDs over bulk EDs. Before processing any of the nonperiodic lists, the
Host Controller must compare the ratio specied with its internal count
on how many nonempty control EDs are processed, in determining
whether to continue serving another control ED or switching to bulk EDs.
The internal count must be retained when crossing the frame boundary.
After a reset, the HCD is responsible for restoring this value.
00b — 1 : 1
01b — 2 : 1
10b — 3 : 1
11b — 4 : 1
Table 46.
HcControl register: bit description …continued
Bit
Symbol
Description