參數資料
型號: ISP1561BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁數: 72/103頁
文件大?。?/td> 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
70 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
Bit
23
22
21
20
19
18
17
16
Symbol
ITC[7:0]
Reset
00001000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
--------
Bit
7
6
5
4
3
2
1
0
Symbol
LHCR
IAAD
ASE
PSE
FLS[1:0]
HC
RESET
RS
Reset
00000000
Access
R/W
Table 104. USBCMD register: bit description
Bit
Symbol
Description
31 to
24
-
reserved
23 to
16
ITC[7:0]
Interrupt Threshold Control: Default 08h. This eld is used by system
software to select the maximum rate at which the Host Controller will issue
interrupts. If software writes an invalid value to this register, the results are
undened. Valid values are:
00h — reserved
01h — 1 micro frame
02h — 2 micro frames
04h — 4 micro frames
08h — 8 micro frames (equals 1 ms)
10h — 16 micro frames (equals 2 ms)
20h — 32 micro frames (equals 4 ms)
40h — 64 micro frames (equals 8 ms)
Software modications to this eld while HCH (HC Halted) bit is zero results in
undened behavior.
15 to 8
-
reserved
7
LHCR
Light Host Controller Reset: This control bit is not required. It allows the
driver software to reset the EHCI controller, without affecting the state of the
ports or the relationship to the companion Host Controllers. If not
implemented, a read of this eld will always return zero. If implemented, on
read:
Logic 0 — Indicates the Light Host Controller Reset has completed and it is
ready for the host software to re-initialize the Host Controller
Logic 1 — Indicates the Light Host Controller Reset has not yet completed
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