參數(shù)資料
型號: ISP1563BM
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁數(shù): 44/102頁
文件大小: 466K
代理商: ISP1563BM
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
46 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
11.1.9 HcControlHeadED register
The HcControlHeadED register contains the physical address of the rst ED of the control
list. The bit allocation is given in Table 59.
Bit
15
14
13
12
11
10
9
8
Symbol
PCED[11:4]
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
PCED[3:0]
reserved
Reset
00000000
Access
RRRRRRRR
Table 58.
HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description
Address: Content of the base address register + 1Ch
Bit
Symbol
Description
31 to 4
PCED[27:0]
Period Current ED: This is used by the Host Controller to point to the head of one of the periodic
lists that must be processed in the current frame. The content of this register is updated by the
Host Controller after a periodic ED is processed. The HCD may read the content in determining
which ED is being processed at the time of reading.
3 to 0
reserved
-
Table 59.
HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit allocation
Address: Content of the base address register + 20h
Bit
31
30
29
28
27
26
25
24
Symbol
CHED[27:20]
Reset
00000000
Access
RRRRRRRR
Bit
23
22
21
20
19
18
17
16
Symbol
CHED[19:12]
Reset
00000000
Access
RRRRRRRR
Bit
15
14
13
12
11
10
9
8
Symbol
CHED[11:4]
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
CHED[3:0]
reserved
Reset
00000000
Access
RRRRRRRR
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