參數(shù)資料
型號(hào): ISP1563BM
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100
文件頁(yè)數(shù): 65/102頁(yè)
文件大?。?/td> 466K
代理商: ISP1563BM
ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
65 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
[1]
The reserved bits should always be written with the reset value.
11.3 EHCI controller capability registers
Other than the OHCI Host Controller, there are some registers in EHCI that dene the
capability of EHCI. The address range of these registers is located before the operational
registers.
11.3.1 CAPLENGTH/HCIVERSION register
The bit allocation of this 4-byte register is given in Table 97.
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
PARITY
TIMEOUT
AUX_OUT_
FULL
INH_SW
CMD_
DATA
FLAG
IN_FULL
OUT_FULL
Reset
00000000
Access
R/W
Table 96.
HceStatus - Host Controller Emulation Status register bit description
Address: Content of the base address register + 10Ch
Bit
Symbol
Description
31 to 8
reserved
-
7
PARITY
Parity: This bit indicates parity error on keyboard and mouse data.
6
TIMEOUT
Time-out: This bit indicates a time-out.
5
AUX_OUT_
FULL
Auxiliary Output Full: IRQ12 is asserted whenever this bit is set to logic 1, OUT_FULL is set to
logic 1, and the IRQEN bit is set.
4
INH_SW
Inhibit Switch: This bit reects the state of the keyboard inhibit switch. If set, the keyboard is
active.
3
CMD_DATA
Cmd Data: The Host Controller sets this bit to logic 0 on an I/O write to port 60h and to logic 1 on
an I/O write to port 64h.
2
FLAG
Flag: Nominally used as a system ag by software to indicate a warm or cold boot.
1
IN_FULL
Input Full: Except in the case of a gate A20 sequence, this bit is set to logic 1 on an I/O write to
address 60h or 64h. While this bit is set to logic 1 and emulation is enabled, an emulation interrupt
condition exists.
0
OUT_FULL
Output Full: The Host Controller sets this bit to logic 0 on a read of I/O port 60h. If IRQEN is set,
AUX_OUT_FULL determines which IRQ is activated. While this bit is logic 0 and C_P in HceControl
is set to logic 1, an emulation interrupt condition exists.
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