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| 型號(hào)： | ISP1563BM |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-100 |
| 文件頁(yè)數(shù)： | 72/102頁(yè) |
| 文件大?。?/td> | 466K |
| 代理商： | ISP1563BM |
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ISP1563_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 15 March 2007
71 of 102
NXP Semiconductors
ISP1563
HS USB PCI Host Controller
11.4.2 USBSTS register
The USB Status (USBSTS) register indicates pending interrupts and various states of the
Host Controller. The status resulting from a transaction on the serial bus is not indicated in
this register. Software clears the register bits by writing ones to them. The bit allocation is
given in Table 105.
[1]
The reserved bits should always be written with the reset value.
1
HCRESET
Host Controller Reset: This control bit is used by the software to reset the Host Controller. The
effects of this on Root Hub registers are similar to a chip hardware reset. Setting this bit causes
the Host Controller to reset its internal pipelines, timers, counters, state machines, and so on, to
their initial value. Any transaction currently in progress on USB is immediately terminated. A USB
reset is not driven on downstream ports. This reset does not affect the PCI Conguration
registers. All operational registers, including port registers and port state machines are set to
their initial values. Port ownership reverts to the companion Host Controller(s). The software must
re-initialize the Host Controller to return it to an operational state. This bit is cleared by the Host
Controller when the reset process is complete. Software cannot terminate the reset process early
by writing logic 0 to this register. Software must check that bit HCH is logic 0 before setting this
bit. Attempting to reset an actively running Host Controller results in undened behavior.
0RS
Run/Stop: 1 = Run. 0 = Stop. When set, the Host Controller executes the schedule. The Host
Controller continues execution as long as this bit is set. When this bit is cleared, the Host
Controller completes the current and active transactions in the USB pipeline, and then halts.
Bit HCH indicates when the Host Controller has nished the transaction and has entered the
stopped state. Software should check that bit HCH is logic 1 before setting this bit.
Table 104. USBCMD - USB Command register bit description …continued
Address: Content of the base address register + 20h
Bit
Symbol
Description
Table 105. USBSTS - USB Status register bit allocation
Address: Content of the base address register + 24h
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
ASS
PSSTAT
RECL
HCH
reserved[1]
Reset
00010000
Access
RRRR
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
IAA
HSE
FLR
PCD
USBERR
INT
USBINT
Reset
00000000
Access
R/W
R
R/W
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1563BM,518 | 功能描述:USB 接口集成電路 USB 2.0 4PORT PCI RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1563BM,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1563BM,557 | 功能描述:USB 接口集成電路 USB 2.0 4PORT PCI HOST CONTROL RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1563BM518 | 制造商:ST-Ericsson 功能描述:CONTROLLER USB PCI HOST 128LQFP |
| ISP1563BMGA | 功能描述:IC USB HOST CTRL HI-SPD 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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