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參數(shù)資料
| 型號： | ISPLSI 2064E-200LT100 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 64I/O 4.5NS 100TQFP |
| 標準包裝： | 90 |
| 系列： | ispLSI® 2000E |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 4.5ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 2000 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI2064E-200LT100 |
9
Specifications ispLSI 2064E
Pin Description
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
GND
2,
13,
25,
38,
51,
63,
74,
88
1,
24,
52,
75
VCC
12,
64
Ground (GND)
VCC
No Connect.
BSCAN
14
TDI/IN 02
16
TMS/IN 12
37
TDO/IN 22
39
TCK/IN 32
60
NC1
10,
26,
27,
49,
50,
61,
76,
77,
89,
99,
100
DESCRIPTION
TQFP PIN NUMBERS
NAME
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 3
17,
18,
19,
20,
I/O 4 - I/O 7
21,
22,
23,
28,
I/O 8 - I/O 11
29,
30,
31,
32,
I/O 12 - I/O 15
33,
34,
35,
36,
I/O 16 - I/O 19
40,
41,
42,
43,
I/O 20 - I/O 23
44,
45,
46,
47,
I/O 24 - I/O 27
48,
53,
54,
55,
I/O 28 - I/O 31
56,
57,
58,
59,
I/O 32 - I/O 35
67,
68,
69,
70,
I/O 36 - I/O 39
71,
72,
73,
78,
I/O 40 - I/O 43
79,
80,
81,
82,
I/O 44 - I/O 47
83,
84,
85,
86,
I/O 48 - I/O 51
90,
91,
92,
93,
I/O 52 - I/O 55
94,
95,
96,
97,
I/O 56 - I/O 59
98,
3,
4,
5,
I/O 60 - I/O 63
6,
7,
8,
9
GOE 0, GOE 1
66,
87
Global Output Enable input pins.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Active Low (0) Reset pin which resets all of the registers in the device.
Y0, Y1, Y2
11,
65,
62
RESET
15
Table 2-0002-2064E.eps
VCCIO
Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must
be connected to the same voltage level.
Input - This pin performs two functions. When
BSCAN is logic low, it
functions as a pin to control the operation of the JTAG state machine.
When
BSCAN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When
BSCAN is logic low, it
functions as an input pin to load programming data into the device.
TDI/IN0 also is used as one of the two control pins for the JTAG state
machine. When
BSCAN is high, it functions as a dedicated input pin.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The TMS, TDI, TDO
and TCK options become active.
Output/Input - This pin performs two functions. When
BSCAN is logic
low, it functions as an output pin to read serial shift register data.
When
BSCAN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When
BSCAN is logic low, it
functions as a clock pin for the Serial Shift Register. When
BSCAN is
high, it functions as a dedicated input pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2064E-200LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064V | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2064V-100LJ44 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2064V-100LJ44I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2064V-100LJ84 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
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