- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1930 > ISPLSI 2064E-200LT100 (Lattice Semiconductor Corporation)IC PLD ISP 64I/O 4.5NS 100TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ISPLSI 2064E-200LT100 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 64I/O 4.5NS 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispLSI® 2000E |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 4.5ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 2000 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI2064E-200LT100 |
2
Specifications ispLSI 2064E
Functional Block Diagram
Figure 1. ispLSI 2064E Functional Block Diagram
TDO/IN 2
Global Routing Pool
(GRP)
A0
A1
A3
Input
Bus
Output
Routing
Pool
(ORP)
B3
B2
B1
B0
Input
Bus
Output
Routing
Pool
(ORP)
A2
CLK
0
CLK
1
CLK
2
GOE
0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
TDI/IN 0
TMS/IN 1
I/O 4
I/O 5
BSCAN
RESET
0139B(1)isp/2064E
I/O
63
I/O
62
I/O
61
I/O
60
I/O
59
I/O
58
I/O
57
I/O
56
I/O
55
I/O
54
I/O
53
I/O
52
I/O
51
I/O
50
I/O
49
I/O
48
Input Bus
Output Routing Pool (ORP)
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
Y0
Y1
Y2
I/O
31
Output Routing Pool (ORP)
Megablock
Input Bus
A4
A5
A6
A7
B7
B6
B5
B4
GOE
1
TCK/IN 3
Generic Logic
Blocks (GLBs)
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control. The signal levels
are TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA. Each output can be pro-
grammed independently for fast or slow output slew rate
to minimize overall output switching noise. By connecting
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by two ORPs. Each
ispLSI 2064E device contains two Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2064E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the Lattice software tools.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI 2064VE-135LTN44 | IC ISP PLD 32I/O 44TQFP |
| ISPLSI 2096A-125LTN128 | IC PLD ISP 96I/O 7.5NS 128TQFP |
| ISPLSI 2096E-180LQ128 | IC PLD ISP 96I/O 5NS 128PQFP |
| ISPLSI 2096VE-200LT128 | IC PLD ISP 96I/O 4.5NS 128TQFP |
| ISPLSI 2128A-100LQN160 | IC PLD ISP 128I/O 10NS 160PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2064E-200LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064V | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2064V-100LJ44 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2064V-100LJ44I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2064V-100LJ84 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。