參數(shù)資料
型號: ISPPAC-CLK5316S-01TN64I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 14/56頁
文件大?。?/td> 0K
描述: IC CLOCK PROGRAM BUFFER 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: ispClock™
類型: 時鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:16
差分 - 輸入:輸出: 是/無
頻率 - 最大: 267MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
Lattice Semiconductor
ispClock5300S Family Data Sheet
21
Figure 14. Input Receiver Termination Conguration
Feedback input is terminated to the VTT_FBK pin through a programmable resistor.
The following usage guidelines are suggested for interfacing to supported logic families.
+
REFA_REFP
REFB_REFN
Differential
Receiver
Single-ended
Receiver
Single-ended
Receiver
To
Internal
Logic
RT
VTT_REFA
VTT_REFB
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