參數(shù)資料
型號(hào): ISPPAC-CLK5316S-01TN64I
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 22/56頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK PROGRAM BUFFER 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: ispClock™
類(lèi)型: 時(shí)鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:16
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 267MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤(pán)
Lattice Semiconductor
ispClock5300S Family Data Sheet
29
Non Zero Delay Buffer Mode 1
In the non zero delay buffer mode as shown in Figure 24 the output routing matrix completely bypasses the PLL.
Each of the single ended input reference clocks can be routed to any number of available output clocks.
In this mode of operation there is no skew control.
Figure 24. Non Zero Delay Fan Out Buffer Mode 1
O
u
tp
u
tRo
u
ting
Matrix
O
u
tp
u
tRo
u
ting
Matrix
O
u
tp
u
tRo
u
ting
Matrix
Single Ended /
Clock Input
REFA_REFP /
REFB_REFN
PLL Bypassed
ispClock5300S
V1
V3
Single Ended /
Clock Input
REFB_REFN /
REFA_REFP
V2
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參數(shù)描述
ISPPACCLK5316S-01TN64I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5320S-01T48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5320S-01T48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5320S-01T64C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5320S-01T64C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended