參數(shù)資料
型號(hào)： ISPPAC-CLK5316S-01TN64I
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 28/56頁(yè)
文件大小： 0K
描述： IC CLOCK PROGRAM BUFFER 64TQFP
標(biāo)準(zhǔn)包裝： 160
系列： ispClock™
類(lèi)型： 時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器
PLL： 帶旁路
輸入： HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL
輸出： eHSTL，HSTL，LVCMOS，LVTTL，SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:16
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 267MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤(pán)
Lattice Semiconductor
ispClock5300S Family Data Sheet
34
Figure 29. External Feedback Mode and Timing Relationships
Other Features
RESET and Power-up Functions
To ensure proper PLL startup and synchronization of outputs, the ispClock5300S provides both internally gener-
ated and user-controllable external reset signals. An internal reset is generated whenever the device is powered
up. An external reset may be applied by asserting a logic LOW at the RESET pin. Asserting RESET resets all inter-
nal dividers, and will cause the PLL to lose lock. On losing lock, the VCO frequency will begin dropping. The length
of time required to regain lock is related to the length of time for which RESET was asserted.
When the ispClock5300S begins operating from initial power-on, the VCO starts running at a very low frequency
(<100 MHz) which gradually increases as it approaches a locked condition. To prevent invalid outputs from being
applied to the rest of the system, assert OEX or OEY high. This will result in the BANK outputs being held in a high-
impedance state until the OEX or OEY pin is pulled LOW.
After in-system programming the device through the JTAG interface, the reset pin must be activated at least for a
period of tPLL_RSTW to reset the device.
If the RESET pin is not driven by an external logic it should be pulled up to VCCD through a 10kΩ resistor.
Software-Based Design Environment
Designers can congure the ispClock5300S using Lattice’s PAC-Designer software, an easy to use, Microsoft Win-
dows compatible program. Circuit designs are entered graphically and then veried, all within the PAC-Designer envi-
ronment. Full device programming is supported using PC parallel port I/O operations and a download cable
connected to the serial programming interface pins of the ispClock5300S. A library of congurations is included with
basic solutions and examples of advanced circuit techniques are available. In addition, comprehensive on-line and
printed documentation is provided that covers all aspects of PAC-Designer operation. PAC-Designer is available for
download from the Lattice web site at www.latticesemi.com. The PAC-Designer schematic window, shown in
Figure 30 provides access to all congurable ispClock5300S elements via its graphical user interface. All analog input
and output pins are represented. Static or non-congurable pins such as power, ground and the serial digital interface
are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu
commands. When completed, congurations can be saved and downloaded to devices.
Input Reference Clock
REF
FBK
BANK
OUTPUT
ispClock5300S
Delay = t
FBK
tφ
t
FBK
REF
FBK
BANK
OUTPUT
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ISPPACCLK5316S-01TN64I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
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ISPPACCLK5320S-01T48I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5320S-01T64C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5320S-01T64C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
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