參數(shù)資料
型號: ISPPAC-CLK5316S-01TN64I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 20/56頁
文件大?。?/td> 0K
描述: IC CLOCK PROGRAM BUFFER 64TQFP
標準包裝: 160
系列: ispClock™
類型: 時鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:16
差分 - 輸入:輸出: 是/無
頻率 - 最大: 267MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 托盤
Lattice Semiconductor
ispClock5300S Family Data Sheet
27
Figure 22. ispClock5300S congured as Zero Delay Buffer Mode
Mixed Zero Delay and Non-Zero Delay Buffer Mode
Figure 23 shows the operation of the ispClock5300S in Mixed Zero Delay and Non Zero Delay modes. In this mode
the output switch matrix is congured to route non selected reference clock, selected reference clock, and the zero
delay clock through the PLL.
The skew control mechanism is available only to clocks sourced from the PLL.
O
u
tp
u
tRo
u
ting
Matrix
External Feedback
Internal Feedback
PLL
Single Ended /
Differential
Clock Input
ispClock5300S
V1
V3
V2
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