- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224103 > K4E640411D-TC500 16M X 4 EDO DRAM, 50 ns, PDSO32 PDF資料下載
參數(shù)資料
| 型號(hào)： | K4E640411D-TC500 |
| 元件分類： | DRAM |
| 英文描述： | 16M X 4 EDO DRAM, 50 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-32 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 407K |
| 代理商： | K4E640411D-TC500 |
CMOS DRAM
K4E660411D, K4E640411D
CAPACITANCE (TA=25
°C, VCC=5.0V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A12]
CIN1
-
5
pF
Input capacitance [RAS, CAS, W, OE]
CIN2
-
7
pF
Output capacitance [DQ0 - DQ3]
CDQ
-
7
pF
AC CHARACTERISTICS (0
°C≤TA≤70°C, See note 1,2)
Test condition : VCC=5.0V
±10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.0/0.8V
Parameter
Symbol
-50
-60
Units
Note
Min
Max
Min
Max
Random read or write cycle time
tRC
84
104
ns
Read-modify-write cycle time
tRWC
116
138
ns
Access time from RAS
tRAC
50
60
ns
3,4,10
Access time from CAS
tCAC
13
15
ns
3,4,5
Access time from column address
tAA
25
30
ns
3,10
CAS to output in Low-Z
tCLZ
3
ns
3
Output buffer turn-off delay from CAS
tCEZ
3
13
3
13
ns
6,14
OE to output in Low-Z
tOLZ
3
ns
3
Transition time (rise and fall)
tT
1
50
1
50
ns
2
RAS precharge time
tRP
30
40
ns
RAS pulse width
tRAS
50
10K
60
10K
ns
RAS hold time
tRSH
13
15
ns
CAS hold time
tCSH
38
45
ns
CAS pulse width
tCAS
8
10K
10
10K
ns
RAS to CAS delay time
tRCD
20
37
20
45
ns
4
RAS to column address delay time
tRAD
15
25
15
30
ns
10
CAS to RAS precharge time
tCRP
5
ns
Row address set-up time
tASR
0
ns
Row address hold time
tRAH
10
ns
Column address set-up time
tASC
0
ns
Column address hold time
tCAH
8
10
ns
Column address to RAS lead time
tRAL
25
30
ns
Read command set-up time
tRCS
0
ns
8
Read command hold time referenced to CAS
tRCH
0
ns
8
Read command hold time referenced to RAS
tRRH
0
ns
Write command hold time
tWCH
10
ns
Write command pulse width
tWP
10
ns
Write command to RAS lead time
tRWL
13
10
ns
Write command to CAS lead time
tCWL
8
10
ns
Data set-up time
tDS
0
ns
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4F640411C-TC500 | 16M X 4 FAST PAGE DRAM, 50 ns, PDSO32 |
| K4F640412C-JC450 | 16M X 4 FAST PAGE DRAM, 45 ns, PDSO32 |
| K4T1G044QC-ZCLE6 | 256M X 4 DDR DRAM, 0.45 ns, PBGA60 |
| K4T56163QI-ZLD50 | 16M X 16 SYNCHRONOUS DRAM, 0.5 ns, PBGA84 |
| K5A3240YT | Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4E640411D-TC60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 4bit CMOS Dynamic RAM with Extended Data Out |
| K4E640412C-TL50 | 制造商:Samsung Semiconductor 功能描述:CMOS DYNAMIC RAM WITH EXTENDED DATA OUT |
| K4E640412C-TL60 | 制造商:Samsung Semiconductor 功能描述:CMOS DYNAMIC RAM WITH EXTENDED DATA OUT |
| K4E640412D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:16M x 4bit CMOS Dynamic RAM with Extended Data Out |
| K4E640412D-TC50 | 制造商:Samsung Semiconductor 功能描述:DRAM Chip EDO 64M-Bit 16Mx4 3.3V 32-Pin TSOP-II |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。