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參數(shù)資料
| 型號(hào)： | K4R271669D-T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit RDRAM(D-die) |
| 中文描述： | 128Mbit的RDRAM（深模） |
| 文件頁(yè)數(shù)： | 16/20頁(yè) |
| 文件大小： | 310K |
| 代理商： | K4R271669D-T |
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Page 14
Direct RDRAM
Preliminary
Version 1.0 Dec. 2001
K4R271669D
Timing Characteristics
Table 12: Timing Characteristics
Symbol
Parameter
Min
Max
Unit
Figure(s)
t
Q
CTM-to-DQA/DQB output time @ t
CYCLE
=2.50ns
-0.310
+0.310
ns
Figure 57
t
QR
, t
QF
DQA/DQB output rise and fall times
0.2
0.45
ns
Figure 57
t
Q1
SCK(neg)-to-SIO0 delay @ C
LOAD,MAX
= 20pF (SD read data valid).
-
10
ns
Figure 60
t
HR
SCK(pos)-to-SIO0 delay @ C
LOAD,MAX
= 20pF (SD read data hold).
2
-
ns
Figure 60
t
QR1
, t
QF1
SIO
OUT
rise/fall @ C
LOAD,MAX
= 20pF
-
5
ns
Figure 60
t
PROP1
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ C
LOAD,MAX
= 20pF
-
10
ns
Figure 60
t
NAPXA
NAP exit delay - phase A
-
50
ns
Figure 49
t
NAPXB
NAP exit delay - phase B
-
40
ns
Figure 49
t
PDNXA
PDN exit delay - phase A
-
4
μ
s
Figure 49
t
PDNXB
PDN exit delay - phase B
-
9000
t
CYCLE
Figure 49
t
AS
ATTN-to-STBY power state delay
-
1
t
CYCLE
Figure 47
t
SA
STBY-to-ATTN power state delay
-
0
t
CYCLE
Figure 47
t
ASN
ATTN/STBY-to-NAP power state delay
-
8
t
CYCLE
Figure 48
t
ASP
ATTN/STBY-to-PDN power state delay
-
8
t
CYCLE
Figure 48
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