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參數(shù)資料
| 型號： | K4R271669D-T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit RDRAM(D-die) |
| 中文描述： | 128Mbit的RDRAM（深模） |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 310K |
| 代理商： | K4R271669D-T |
Page 17
Direct RDRAM
Preliminary
Version 1.0 Dec. 2001
K4R271669D
Capacitance and Inductance
Table 17: RSL Pin Parasitics
Symbol
Parameter and Conditions - RSL pins
Min
Max
Unit
Figure
L
I
RSL effective input inductance
4.0
nH
Figure 62
L
12
Mutual inductance between any DQA or DQB RSL signals
0.6
nH
Figure 62
Mutual inductance between any ROW or COL RSL signals
0.6
L
I
Difference in L
I
value between any RSL pins of a single device.
-
2.0
nH
Figure 62
C
I
RSL effective input capacitance
a
2.0
2.6
pF
Figure 62
C
12
Mutual capacitance between any RSL signals.
-
0.2
pF
Figure 62
C
I
Difference in C
I
value between average of {CTM, CTMN, CFM,
CFMN} and any RSL pins of a single device
0.12
pF
Figure 62
R
I
RSL effective input resistance
4
18
Figure 62
a. This value is a combination of the device IO circuitry and package capacitances measured at VDD=2.5V and f=400MHz with pin biased at 1.4V.
Table 18: CMOS Pin Parasitics
Symbol
Parameter and Conditions - CMOS pins
Min
Max
Unit
Figure
L
I ,CMOS
CMOS effective input inductance
8.0
nH
Figure 62
C
I ,CMOS
CMOS effective input capacitance (SCK,CMD)
a
1.7
2.1
pF
C
I ,CMOS,SIO
CMOS effective input capacitance (SIO1, SIO0)
a
-
7.0
pF
a. This value is a combination of the device IO circuitry and package capacitances.
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