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Direct RDRAM
Preliminary
Version 1.0 Dec. 2001
K4R271669D
Overview
The Rambus Direct RDRAM is a general purpose high-
performance memory device suitable for use in a broad
range of applications including communications, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 128Mbit Direct Rambus DRAMs (RDRAM
) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16. The use of Rambus Signaling Level (RSL)
technology permits to 800MHz transfer rates while using
conventional system and board design technologies. Direct
RDRAM devices are capable of sustained data transfers at
1.25 ns per two bytes (10ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and communi-
cations include power management, byte masking.
Features
Highest sustained bandwidth per DRAM device
-
1.6
GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
Advanced power management:
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
Organization: 1Kbyte pages and 32 banks, x 16
- x16 organization for low cost applications
Uses Rambus Signaling Level (RSL) for up to 800MHz
operation
WBGA package(54 Balls)
The 128Mbit Direct RDRAMs are offered in a horizontal
center-bond fanout CSP.
Key Timing Parameters/Part Numbers
Figure 1: Direct RDRAM CSP Package
Organiza-
tion
Speed
Part Number
Bin
I/O
Freq.
MHz
t
RAC
(Row
Time) ns
256Kx16x32s
a
a.
“
32s
”
- 32 banks which use a
“
split
”
bank architecture.
b.
“
T
”
- Lead free consumer package.
-CS8
800
45
K4R271669D-T
b
CS8
K4R271669D-T
C
xx
SAMSUNG
001