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參數(shù)資料
| 型號(hào)： | K4T1G084QQ-HC(L)F7 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb Q-die DDR2 SDRAM Specification |
| 中文描述： | 1Gb的調(diào)Q DDR2內(nèi)存芯片規(guī)格 |
| 文件頁數(shù)： | 40/44頁 |
| 文件大?。?/td> | 891K |
| 代理商： | K4T1G084QQ-HC(L)F7 |
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K4T1G084QQ
K4T1G164QQ
Rev. 1.01 November 2007
DDR2 SDRAM
40 of 44
K4T1G044QQ
20.
Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the VIH(ac) level to the
differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for
a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18.
21.
Input waveform timing tDH with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input sig-
nal crossing at the VIH(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for
a rising signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(dc)max and Vih(dc)min. See Figure 18.
22.
Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal and VIL(ac) for a falling signal applied to the
device under test. See Figure 19.
23.
Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal and VIH(dc) for a falling signal applied to the
device under test. See Figure 19.
tDS
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
V
SS
DQS
DQS
tDH
tDS
tDH
Figure 18 - Differential input waveform timing - tDS and tDH
tIS
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF(dc)
V
IL(dc)
max
V
IL(ac)
max
V
SS
CK
CK
tIH
tIS
tIH
Figure 19 - Differential input waveform timing - tIS and tIH
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