參數(shù)資料
型號： K4T56163QI-ZLD50
元件分類： DRAM
英文描述： 16M X 16 SYNCHRONOUS DRAM, 0.5 ns, PBGA84
封裝： ROHS COMPLIANT, FBGA-84
文件頁數(shù)： 15/42頁
文件大?。?/td> 727K
代理商： K4T56163QI-ZLD50
Rev. 1.0 October 2007
DDR2 SDRAM
K4T56163QI
22 of 42
Table 3 - DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the
tDS and tDH derating value respectively. Example: tDS (total setup time) =tDS(base) +tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min.
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If
the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(dc) to ac region’, use nominal slew rate for derating value (See
Figure 5 for differential data strobe and Figure 6 for single-ended data strobe.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ’VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see
Figure 7 for differential data strobe and Figure 8 for single-ended data strobe)
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing of VREF(dc). Hold
(tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first crossing of VREF(dc). If the
actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(dc) region’, use nominal slew rate for derating value (see
Figure 9 for differential data strobe and Figure 10 for single-ended data strobe) If the actual signal is earlier than the nominal slew rate line anywhere
between shaded ’dc to VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value
(see Figure 11 for differential data strobe and Figure 12 for single-ended data strobe)
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in Tables 1, 2 and 3, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
tDS1, tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table)
DQS Single-ended Slew Rate
2.0 V/ns
1.5 V/ns
1.0 V/ns
0.9 V/ns
0.8 V/ns
0.7 V/ns
0.6 V/ns
0.5 V/ns
0.4 V/ns
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
tDS
1
tDH
1
DQ
Slew
rate
V/ns
2.0
188
167
146
125
63
-
1.5
146
167
125
83
42
81
43
-
1.0
63
125
42
83
0
-2
1
-7
-13
--
0.9
-
31
69
-11
-14
-13
-18
-27
-29
-45
-
0.8
-
-25
-31
-27
-30
-32
-44
-43
-62
-60
-86
-
0.7
-
-45
-53
-50
-67
-61
-85
-78
-109
-108
-152
-
0.6
-
-74
-96
-85
-114
-102
-138
-181
-183
-246
0.5
-
-128
-156
-145
-180
-175
-223
-226
-288
0.4
---
--
---
-210
-243
-240
-286
-291
-351
相關(guān)PDF資料
PDF描述
K5A3240YT Multi-Chip Package MEMORY 32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 4M(512Kx8/256Kx16) Full CMOS SRAM
K6R1004C1C 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
K6R1004C1C-I 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
K6R1004C1C-I10 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
K6R1004C1C-I12 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating).
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4T56163QN 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Consumer Memory
K4T56163QN-HCE6000 制造商:Samsung SDI 功能描述:DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin FBGA Tray
K4T56163QN-HCE6T00 制造商:Samsung SDI 功能描述:
K4T56163QN-ZCE6T00 制造商:Samsung 功能描述:256 SDRAM X16 - Tape and Reel
K4T56163QN-ZCE7000 制造商:Samsung 功能描述:DDR2 SDRAM 32MX16 47H32M16 PBF FBGA 1.8V PLASTIC 512M - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*