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參數(shù)資料
| 型號(hào)： | K7I161882B-FC30 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| 中文描述： | 512Kx36位，1Mx18位首席信息官b2條DDRII的SRAM |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 378K |
| 代理商： | K7I161882B-FC30 |
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
- 2 -
Rev 3.1
July. 2004
K7I163682B
K7I161882B
512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
FEATURES
1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future
freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O
.
Pipelined, double-data rate operation.
Common data input/output bus .
HSTL I/O
Full data coherency, providing most current data.
Synchronous pipeline read with self timed late write.
Registered address, control and data input/output.
DDR(Double Data Rate) Interface on read and write ports.
Fixed 2-bit burst for both read and write operation.
Clock-stop supports to reduce current.
Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
Two echo clocks (CQ and CQ) to enhance output data
traceability.
Single address bus.
Byte write (x18, x36) function.
Simple depth expansion with no data contention.
Programmable output impedance.
JTAG 1149.1 compatible test access port.
165FBGA(11x15 ball array FBGA) with body size of 13x15mm
FUNCTIONAL BLOCK DIAGRAM
LD
R/W
BW
X
ADDRESS
A0
C
C
ADD REG
&
BURST
LOGIC
DATA
REG
CLK
GEN
CTRL
LOGIC
512Kx36
(1Mx18)
MEMORY
ARRAY
WRITE DRIVER
K
K
4(or 2)
DQ
SELECT OUTPUT CONTROL
S
W
O
O
O
Notes
: 1. Numbers in ( ) are for x18 device.
18
18 (or 19)
36 (or 18)
36
72
(Echo Clock out)
CQ, CQ
Organization
Part
Number
Cycle
Time
Access
Time
Unit
X36
K7I163682B-FC30
3.3
0.45
ns
K7I163682B-FC25
4.0
0.45
ns
K7I163682B-FC20
5.0
0.45
ns
K7I163682B-FC16
6.0
0.50
ns
X18
K7I161882B-FC30
3.3
0.45
ns
K7I161882B-FC25
4.0
0.45
ns
K7I161882B-FC20
5.0
0.45
ns
K7I161882B-FC16
6.0
0.50
ns
36 (or 18)
DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
(or 19)
(or 18)
(or 36)
36 (or 18)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7I163682B | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| K7I163682B-FC16 | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| K7I163682B-FC20 | GT 35C 35#16 PIN PLUG RTANG |
| K7I163682B-FC25 | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| K7I163682B-FC30 | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7I161884B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 DDRII CIO b4 SRAM |
| K7I161884B-FC25T00 | 制造商:Samsung Semiconductor 功能描述:16MSYNC DDRII, COMMON I/O SRAM 1MX18FBGA, T/R - Tape and Reel |
| K7I163682B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| K7I163682B_06 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 DDRII CIO b2 SRAM |
| K7I163682B-FC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
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