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    參數(shù)資料
    型號(hào)： K7I161882B-FC30
    廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
    英文描述： 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
    中文描述： 512Kx36位，1Mx18位首席信息官b2條DDRII的SRAM
    文件頁(yè)數(shù)： 3/17頁(yè)
    文件大?。?/td> 378K
    代理商： K7I161882B-FC30
    512Kx36 & 1Mx18 DDRII CIO b2 SRAM
    - 3 -
    Rev 3.1
    July. 2004
    K7I163682B
    K7I161882B
    PIN CONFIGURATIONS
    (TOP VIEW)
    K7I163682B(512Kx36)
    Notes :
    1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb, 2A for 144Mb .
    2. BW
    0
    controls write to DQ0:DQ8, BW
    1
    controls write to DQ9:DQ17, BW
    2
    controls write to DQ18:DQ26 and BW
    3
    controls write to DQ27:DQ35.
    1
    2
    3
    4
    5
    6
    K
    7
    8
    9
    10
    11
    CQ
    A
    CQ
    V
    SS/
    SA*
    NC
    R/W
    BW
    2
    BW
    1
    LD
    SA
    V
    SS/
    SA*
    B
    C
    D
    NC
    NC
    NC
    DQ27
    NC
    DQ29
    DQ18
    DQ28
    DQ19
    SA
    V
    SS
    V
    SS
    BW
    3
    SA
    V
    SS
    K
    BW
    0
    SA
    V
    SS
    SA
    V
    SS
    V
    SS
    NC
    NC
    NC
    NC
    DQ17
    NC
    DQ8
    DQ7
    DQ16
    SA0
    V
    SS
    E
    F
    G
    NC
    NC
    NC
    NC
    DQ30
    DQ31
    DQ20
    DQ21
    DQ22
    V
    DDQ
    V
    DDQ
    V
    DDQ
    V
    SS
    V
    DD
    V
    DD
    V
    SS
    V
    SS
    V
    SS
    V
    SS
    V
    DD
    V
    DD
    V
    DDQ
    V
    DDQ
    V
    DDQ
    NC
    NC
    NC
    DQ15
    NC
    NC
    DQ6
    DQ5
    DQ14
    H
    J
    K
    Doff
    NC
    NC
    V
    REF
    NC
    NC
    V
    DDQ
    DQ32
    DQ23
    V
    DDQ
    V
    DDQ
    V
    DDQ
    V
    DD
    V
    DD
    V
    DD
    V
    SS
    V
    SS
    V
    SS
    V
    DD
    V
    DD
    V
    DD
    V
    DDQ
    V
    DDQ
    V
    DDQ
    V
    DDQ
    NC
    NC
    V
    REF
    DQ13
    DQ12
    ZQ
    DQ4
    DQ3
    L
    M
    N
    P
    NC
    NC
    NC
    NC
    DQ33
    NC
    DQ35
    NC
    DQ24
    DQ34
    DQ25
    DQ26
    V
    DDQ
    V
    SS
    V
    SS
    SA
    V
    SS
    V
    SS
    SA
    SA
    V
    SS
    V
    SS
    SA
    C
    V
    SS
    V
    SS
    SA
    SA
    V
    DDQ
    V
    SS
    V
    SS
    SA
    NC
    NC
    NC
    NC
    NC
    DQ11
    NC
    DQ9
    DQ2
    DQ1
    DQ10
    DQ0
    R
    TDO
    TCK
    SA
    SA
    SA
    C
    SA
    SA
    SA
    TMS
    TDI
    PIN NAME
    Notes:
    1. C, C, K or K cannot be set to V
    REF
    voltage.
    2. When ZQ pin is directly connected to V
    DD
    output impedance is set to minimum value
    and it
    cannot be connected to ground or left unconnected
    .
    3. Not connected to chip pad internally.
    SYMBOL
    K, K
    C, C
    PIN NUMBERS
    6B, 6A
    6P, 6R
    DESCRIPTION
    Input Clock
    Input Clock for Output Data
    NOTE
    1
    CQ, CQ
    Doff
    SA0
    11A, 1A
    1H
    6C
    Output Echo Clock
    DLL Disable when low
    Burst Count Address Inputs
    SA
    9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
    2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
    11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
    3M,10M,11M,2N,3N,11N,3P,10P,11P
    Address Inputs
    DQ0-35
    Data Inputs Outputs
    R/W
    4A
    Read, Write Control Pin, Read active
    when high
    LD
    8A
    Synchronous Load Pin, bus Cycle
    sequence is to be defined when low
    BW
    0
    , BW
    1,
    BW
    2
    , BW
    3
    7B,7A,5A,5B
    Block Write Control Pin,active when low
    V
    REF
    ZQ
    V
    DD
    V
    DDQ
    2H,10H
    11H
    Input Reference Voltage
    Output Driver Impedance Control Input
    Power Supply ( 1.8 V )
    Output Power Supply ( 1.5V or 1.8V )
    2
    5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
    4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
    V
    SS
    2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
    4M-8M,4N,8N
    Ground
    TMS
    TDI
    TCK
    10R
    11R
    2R
    JTAG Test Mode Select
    JTAG Test Data Input
    JTAG Test Clock
    TDO
    1R
    JTAG Test Data Output
    NC
    3A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
    1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
    1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
    No Connect
    3
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