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參數(shù)資料
| 型號： | K7I161882B-FC30 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| 中文描述： | 512Kx36位，1Mx18位首席信息官b2條DDRII的SRAM |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 378K |
| 代理商： | K7I161882B-FC30 |
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
- 4 -
Rev 3.1
July. 2004
K7I163682B
K7I161882B
PIN CONFIGURATIONS
(TOP VIEW)
K7I161882B(1Mx18)
Notes:
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 72Mb.
2. BW
0
controls write to DQ0:DQ8 and BW
1
controls write to DQ9:DQ17.
PIN NAME
1
2
3
4
5
6
K
K
7
8
9
10
Vss
NC
11
CQ
DQ8
A
B
CQ
NC
V
SS/
SA*
DQ9
SA
NC
R/W
SA
BW
1
NC
NC
BW
0
LD
SA
SA
NC
C
D
E
NC
NC
NC
NC
NC
NC
NC
DQ10
DQ11
V
SS
V
SS
V
DDQ
SA
V
SS
V
SS
SA0
V
SS
V
SS
SA
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC
NC
NC
DQ7
NC
NC
NC
NC
DQ6
F
G
H
NC
NC
Doff
DQ12
NC
V
REF
NC
DQ13
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
V
DDQ
NC
NC
V
DDQ
NC
NC
V
REF
DQ5
NC
ZQ
J
K
L
NC
NC
NC
NC
NC
DQ15
NC
DQ14
NC
V
DDQ
V
DDQ
V
DDQ
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DDQ
V
DDQ
V
DDQ
NC
NC
NC
DQ4
NC
NC
NC
DQ3
DQ2
M
N
P
R
NC
NC
NC
TDO
NC
NC
NC
TCK
NC
DQ16
DQ17
SA
V
SS
V
SS
SA
SA
V
SS
SA
SA
SA
V
SS
SA
C
C
V
SS
SA
SA
SA
V
SS
V
SS
SA
SA
NC
NC
NC
SA
DQ1
NC
NC
TMS
NC
NC
DQ0
TDI
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value
and it
cannot be connected to ground or left unconnected
.
3. Not connected to chip pad internally.
SYMBOL
K, K
PIN NUMBERS
6B, 6A
DESCRIPTION
Input Clock
NOTE
C, C
CQ, CQ
Doff
6P, 6R
11A, 1A
1H
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
1
SA0
SA
6C
Burst Count Address Inputs
Address Inputs
3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P
DQ0-17
Data Inputs Outputs
R/W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW
0
, BW
1
7B, 5A
Block Write Control Pin,active when low
V
REF
ZQ
V
DD
2H,10H
11H
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
2
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
V
DDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
V
SS
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
TMS
TDI
TCK
10R
11R
2R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
TDO
1R
JTAG Test Data Output
NC
7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D
1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P
No Connect
3
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