- 您現(xiàn)在的位置：買賣IC網 > PDF目錄224103 > K7N403609B-QI22 128K X 36 ZBT SRAM, 2.6 ns, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | K7N403609B-QI22 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 2.6 ns, PQFP100 |
| 封裝： | 20 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 398K |
| 代理商： | K7N403609B-QI22 |
K7N403609B
128Kx36/x32 & 256Kx18 Pipelined N
tRAM
TM
- 6 -
Rev 1.0
November 2001
K7N401809B
K7N403209B
FUNCTION DESCRIPTION
The K7N4036/3209B and K7N401809B are NtRAM TM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE , LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE ) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
N tRAM TM latches external address and initiates a cycle, when CKE , ADV are driven to low and all three chip enables(CS1
, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW [d:a] can be used for byte write operation. The pipe-
lined NtRAM TM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO =High)
Note :
1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
LBO PIN
HIGH
Case 1
Case 2
Case 3
Case 4
A 1
A 0
A 1
A 0
A 1
A 0
A 1
A 0
First Address
Fourth Address
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
BQ TABLE
(Linear Burst, LBO=Low)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
LBO PIN
LOW
Case 1
Case 2
Case 3
Case 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
Fourth Address
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
相關PDF資料 |
PDF描述 |
|---|---|
| K7Q161854A-FC20 | 1M X 18 QDR SRAM, 2.2 ns, PBGA165 |
| K7R161884B | 512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R163684B | 512Kx36 & 1Mx18 QDR II b4 SRAM |
| K7R323682 | 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM |
| K971 | 85.05 mm2, COPPER ALLOY, TIN FINISH, RING TERMINAL |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K7N420 PRO | 制造商:Micro-Star International 功能描述:SOCKET A MOTHERBOARD - Bulk |
| K7N420 PRO RPL | 制造商:Micro-Star International 功能描述:SOCKET A MOTHERBOARD - Bulk |
| K7N420 PRO-DF | 制造商:Micro-Star International 功能描述:SOCKET A MOTHERBOARD - Bulk |
| K7N4240 PRO-DF | 制造商:Micro-Star International 功能描述:SOCKET A MOTHERBOARD - Bulk |
| K7N641845M | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2Mx36 & 4Mx18 Pipelined NtRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。