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參數(shù)資料
| 型號： | K7N403609B-QI22 |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 2.6 ns, PQFP100 |
| 封裝： | 20 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 398K |
| 代理商： | K7N403609B-QI22 |
K7N403609B
128Kx36/x32 & 256Kx18 Pipelined NtRAMTM
- 7 -
Rev 1.0
November 2001
K7N401809B
K7N403209B
STATE DIAGRAM FOR NtRAMTM
BEGIN
WRITE
BURST
WRITE
BEGIN
READ
WRITE
DS
RE
AD
BURST
READ
DS
WR
ITE
DS
READ
DS
R
E
A
D
S
W
R
IT
E
B
U
R
S
T
DESELECT
B
U
R
S
T
R
E
A
D
B
U
R
S
T
W
R
IT
E
READ
WRITE
BURST
Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does
not change the state of the device.
2. States change on the rising edge of the clock(CLK)
COMMAND
ACTION
DS
DESELECT
READ
BEGIN READ
WRITE
BEGIN WRITE
BURST
BEGIN READ
BEGIN WRITE
CONTINUE DESELECT
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