參數(shù)資料
型號(hào)： K9S1208V0M-SSB0
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 64M x 8 Bit SmartMedia Card
中文描述： 6400 × 8位SmartMedia卡
文件頁(yè)數(shù)： 4/33頁(yè)
文件大?。?/td> 491K
代理商： K9S1208V0M-SSB0
K9S1208V0M-SSB0
SmartMedia
TM
4
Product Introduction
The K9S1208V0M is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen col-
umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating
data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of
16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the
32 pages formed by two NAND structures, totaling 8,192 NAND structures of 16 cells. The array organization is shown in Figure 2.
The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The mem-
ory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9S1208V0M.
The K9S1208V0M has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires
26 addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in that
order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase
operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into
the command register. Table 1 defines the specific commands of the K9S1208V0M.
The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into four 128Mbit
separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining
the conventional 512 byte structure.
The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of
selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.
Table 1. Command Sets
NOTE
: 1. The 00h command defines starting address of the 1st half of registers.
The 01h command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
Function
1st. Cycle
2nd. Cycle
3rd. Cycle
Acceptable Command
Read 1
00h/01h
(1)
-
-
Read 2
50h
-
-
Read ID (1)
90h
-
-
Read ID (2)
91h
-
-
Reset
FFh
-
-
O
Page Program (True)
80h
10h
-
Page Program (Dummy)
80h
11h
-
Page Program (Multi Block Program)
80h
15h
-
Block Erase
60h
D0h
-
Multi-Plane Block Erase
60h---60h
D0h
-
Read Status
70h
-
-
O
Read Multi-Plane Status
71h
(2)
-
-
O
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