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K9S1208V0M-SSB0
SmartMedia
TM
8
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
Mode
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input(4clock)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input(4clock)
L
L
L
H
H
Data Input
L
L
L
H
X
sequential Read & Data Output
L
L
L
H
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
Stand-by
CAPACITANCE
(
T
A
=25
°
C, V
CC
=3.3V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
VALID BLOCK
NOTE
:
1. The
K9S1208V0M
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
.
Do not try
to access these invalid blocks for program and erase.
Refer to the attached technical notes for a appropriate management of invalid blocks.
2. Per the specification of the physical format version 1.2 by SSFDC forum, minimum 1,000 vaild blocks are guaranteed for each 16MB memory space.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
4026
-
4096
Blocks
AC TEST CONDITION
(T
A
=0 to 55
°
C, V
CC
=2.7V~3.6V unless otherwise noted)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load (3.0V +/-10%)
1 TTL GATE and CL=50pF
Output Load (3.3V +/-10%)
1 TTL GATE and CL=100pF
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
-
200
500
μ
s
μ
s
Dummy Busy Time for Multi Plane Program
t
DBSY
1
10
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
1
cycle
Spare Array
-
-
2
cycles
Block Erase Time
t
BERS
-
2
3
ms