參數(shù)資料
型號(hào)： KAD5610P-25Q72
廠商： Intersil
文件頁(yè)數(shù)： 16/30頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 250MSPS DUAL 72-QFN
產(chǎn)品培訓(xùn)模塊： High-Speed Analog-to-Digital Converters
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 10
采樣率（每秒）： 250M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 438mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，單極
23
FN6810.2
September 10, 2009
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two ADCs cores. The nominal range and
resolution of this adjustment are given in Table 11. The
default value of this register after power-up is 00h.
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine the
synchronization of the incoming and divided clock phases. This
is particularly important when multiple ADCs are used in a time-
interleaved system. The phase slip feature allows the rising
edge of the divided clock to be advanced by one input clock
cycle when in CLK/4 mode, as shown in Figure 40. Execution
of a phase_slip command is accomplished by first writing a ‘0’
to bit 0 at address 71h followed by writing a ‘1’ to bit 0 at
address 71h (32 sclk cycles).
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5610P has a selectable clock divider that can be
set to divide by four, two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input”
on page 16). This functionality can be overridden and
controlled through the SPI, as shown in Table 12. This
register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5610P can present output data in two physical formats:
LVDS or LVCMOS. Additionally, the drive strength in LVDS
mode can be set high (3mA) or low (2mA). By default, the
tri-level OUTMODE pin selects the mode and drive level
(refer to “Digital Outputs” on page 17). This functionality can
be overridden and controlled through the SPI, as shown in
Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 18). This functionality can be overridden
and controlled through the SPI, as shown in Table 14.
This register is not changed by a Soft Reset.
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or
slow.
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 15 shows
the allowable sample rate ranges for the slow and fast
settings.
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
PARAMETER
0X70[7:0]
DIFFERENTIAL SKEW
Steps
256
–Full Scale (0x00)
-6.5ps
Mid–Scale (0x80)
0.0ps
+Full Scale (0xFF)
+6.5ps
Nominal Step Size
51fs
TABLE 12. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
FIGURE 40. PHASE SLIP: CLK
÷4 MODE, fCLOCK = 1000MHz
CLK
÷
CLK
÷
SLIP ONCE
CLK = CLKP
CLKN
CLK
÷
SLIP TWICE
1.00ns
4.00ns
010
Divide by 2
100
Divide by 4
TABLE 13. OUTPUT MODE CONTROL
VALUE
0x93[7:5]
OUTPUT MODE
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
TABLE 14. OUTPUT FORMAT CONTROL
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
TABLE 12. CLOCK DIVIDER SELECTION (Continued)
VALUE
0x72[2:0]
CLOCK DIVIDER
KAD5610P
相關(guān)PDF資料
PDF描述
KAD5612P-17Q72 IC ADC 12BIT 170MSPS DUAL 72-QFN
LA72715NV-TLM-E IC AUDIO DECODER JPN MTS 24SSOP
LICAL-DEC-LS001 IC DECODER LOW SECURITY 8DIP
LICAL-DEC-MS001 IC DECODER MS SERIES 20-SSOP
LICAL-ENC-MS001 IC ENCODER MS SERIES 20-SSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KAD5612P 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Dual 12-Bit, 250/210/170/125MSPS A/D Converter
KAD5612P_09 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Dual 12-Bit, 250/210/170/125MSPS A/D Converter
KAD5612P_0909 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Dual 12-Bit, 250/210/170/125MSPS A/D Converter
KAD5612P-12Q72 功能描述:IC ADC 12BIT 125MSPS DUAL 72-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:FemtoCharge™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類(lèi)型:2 個(gè)單端，單極
KAD5612P-17Q72 功能描述:IC ADC 12BIT 170MSPS DUAL 72-QFN RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:FemtoCharge™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類(lèi)型:2 個(gè)單端，單極
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*