參數(shù)資料
型號： KIT33689DWBEVB
廠商： Freescale Semiconductor
文件頁數(shù)： 16/31頁
文件大?。?/td> 0K
描述： KIT FOR 33689 SBC WITH LIN
標(biāo)準(zhǔn)包裝： 1
主要目的： LIN 接口
已用 IC / 零件： MC33689
相關(guān)產(chǎn)品： MC33689DDWBR2CT-ND - IC SYSTEM BASE W/LIN 32-SOIC
MC33689DWBR2-ND - IC SYSTEM BASE W/LIN 32-SOIC
MC33689DWB-ND - IC SYSTEM BASE W/LIN 32-SOIC
MC33689DDWBR2TR-ND - IC SYSTEM BASE W/LIN 32-SOIC
MC33689DDWB-ND - IC SYSTEM BASE W/LIN 32-SOIC
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
33689
FUNCTIONAL DESCRIPTION
FUNCTIONAL DEVICE OPERATION
NORMAL MODE
In Normal Mode, the 33689 has slew rate and timing
compatible with the LIN protocol specification. The LIN bus
can transmit and receive information. The VDD regulator is
ON and the watchdog function can be enabled.
SLEEP AND STOP MODE
To safely enter Sleep or Stop modes and to ensure that
these modes are not inadvertently entered due to noise
issues during SPI transmission, a dedicated sequence must
be sent twice: data with the bits controlling the LIN bus and
the device mode.
Entering Sleep Mode
First and second SPI commands (with bit D6=1, D7=1,
D5 =0 or 1, D1=0, and D0=0) 11x00000 must be sent.
Entering Stop Mode
First and second SPI commands (with bit D6=1, D7=1,
D5 =0 or 1, D1=0, and D0=1) 11x00001 must be sent.
Sleep or Stop modes are entered after the second SPI
command. Register bit D5 must be set accordingly.
Table 1. Operational Modes and Associated Functions
Device Mode
VDD Voltage
Regulator
Wake-Up
Capabilities
RST
Output
Watchdog
Function
HS1, HS2, HS3
LIN Interface
Operational
Amplifier
Reset
VDD: ON
N/A
LOW for 1.0 ms
typical, then
HIGH (if VDD
above threshold)
Disabled
OFF
Recessive only
Not active
Normal
Request
VDD: ON
N/A
HIGH.
Active LOW if
VDD
undervoltage
occurs and if
Normal Request
timeout (if
Watchdog
enabled)
150 ms timeout
if Watchdog
enabled
ON or OFF
Transmit and
receive
Not active
Normal
VDD: ON
N/A
HIGH.
Active LOW if
VDD
undervoltage
occurs or if
Watchdog fail (if
Watchdog
enabled)
Window
Watchdog if
enabled
ON or OFF
Transmit and
receive
Active
Stop
VDD: ON
(Limited current
capability)
LIN and state
change on
L1:L2 inputs
Normally HIGH.
Active LOW if
VDD
undervoltage
occurs
Disabled
OFF
Recessive state
with Wake
capability
Not active
Sleep
VDD: OFF
(Set to 5.0 V
after Wake-Up
to enter Normal
Request)
LIN and state
change on
L1:L2 inputs
LOW.
Go to HIGH after
Wake-Up and
VDD within
specification
Disabled
OFF
Recessive state
with Wake
capability
Not active
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