參數(shù)資料
型號(hào): KIT33689DWBEVB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 8/31頁(yè)
文件大小: 0K
描述: KIT FOR 33689 SBC WITH LIN
標(biāo)準(zhǔn)包裝: 1
主要目的: LIN 接口
已用 IC / 零件: MC33689
相關(guān)產(chǎn)品: MC33689DDWBR2CT-ND - IC SYSTEM BASE W/LIN 32-SOIC
MC33689DWBR2-ND - IC SYSTEM BASE W/LIN 32-SOIC
MC33689DWB-ND - IC SYSTEM BASE W/LIN 32-SOIC
MC33689DDWBR2TR-ND - IC SYSTEM BASE W/LIN 32-SOIC
MC33689DDWB-ND - IC SYSTEM BASE W/LIN 32-SOIC
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
33689
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 5. Test Circuit for Timing Measurements
Figure 6. SPI Timing Characteristics
TXD
RXD
33689
VS1/VS2
LIN
VPWR
R0
C0
R0/C0 Combinations:
1.0 k
Ω/1.0 nF
660
Ω/6.8 nF
500
Ω/10 nF
GND
TGND AGND
DI 0
DO 0
Undefined
Don’t Care
DI 7
Don’t Care
tLEAD
tSI(HOLD)
tSI(SU)
tLAG
tPSCLK
tWSCLKH
tWSCLKL
tVALID
DO 7
tSO(DIS)
CS
SCLK
MOSI
MISO
tSO(EN)
Note Incoming data at MOSI pin is sampled by the 33689 at SCLK falling edge. Outgoing data at MISO is set by the 33689
at SCLK rising edge (after tVALID delay time).
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