參數(shù)資料
型號: KM416S1020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512K x 16Bit x 2 Banks Synchronous DRAM(512K x 16位 x 2組同步動態(tài)RAM)
中文描述: 為512k × 16 × 2銀行同步DRAM(為512k × 16位× 2組同步動態(tài)RAM)的
文件頁數(shù): 1/42頁
文件大小: 582K
代理商: KM416S1020C
KM416S1020C
CMOS SDRAM
- 2 -
Rev. 0.4 (Apr. 1998)
Revision History
Revision 0.4 (April 17, 1998)
Changed DC/AC Test Output Load from 30pF to 50pF in
AC OPERATING TEST CONDITIONS
.
Changed tOH from 2.5ns to 3ns in KM416S1020C-8/H/L/10 in
AC CHARACTERISTICS
.
Revision 0.3 (April 2, 1998)
Changed DC/AC Test Output Load from 50pF to 30pF in
AC OPERATING TEST CONDITIONS
.
Changed tSAC from 6ns to 7ns, tSHZ from 6ns to 7ns @ CL=2 in KM416S1020C-8, tOH from 3ns to 2.5ns in
KM416S1020C-8/H/L/10 in
AC CHARACTERISTICS
.
Revision 0.2 (February 1998)
Input Leakage Currents (Inputs / DQ) are changed(IIL(Inputs) :
±
5uA to
±
1uA, IIL(DQ) :
±
5uA to
±
1.5uA.).
Cin to be measured at VDD = 3.3V, TA = 23
°
C, f = 1MHz, VREF =1.4V
±
200 mV.
Bining -7 is added.
Refresh cycle changed 2K/32ms to 4K/64ms.
AC Operating Condition is changed as defined :
- VIH(max) = 5.6V AC. The overshoot voltage duration is
3ns.
- VIL(min) = -2.0V AC. The undershoot voltage duration is
3ns.
Revision 0.1 (November 1997)
tRDL has changed 10ns to 12ns.
相關(guān)PDF資料
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KM416S1021C 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interfacer(512K x 16位 x 2組同步動態(tài)RAM(帶SSTL接口))
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