參數(shù)資料
型號(hào)： KM432C515
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512K x 32Bit CMOS Quad CAS DRAM with EDO(512K x 32位CMOS四 CAS 動(dòng)態(tài)RAM(帶EDO模式))
中文描述： 為512k × 32Bit的中科院的CMOS四路DRAM與江戶（512k × 32的位的CMOS四中科院動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶EDO公司模式））
文件頁(yè)數(shù)： 7/21頁(yè)
文件大?。?/td> 361K
代理商： KM432C515
CMOS DRAM
KM432C515, KM432V515
REV. 0.
Apr. 1998
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Transition times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 1 TTL load and 50pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min),
t
AWD
≥
t
AWD
(min) and
t
CPWD
≥
t
CPWD
(min), then the cycle is a read-
modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write
cycle and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
t
ASC
≥
6ns, Assume
t
T
= 2.0ns.
In order to hold the address latched by the first CAS going low, the parameter t
CLCH
must be met.
The last CASx edge to go low.
The last CASx edge to go high.
The first CASx edge to go low.
The first CASx edge to go high.
Output parameter is refrenced to corresponding CASx input.
The last rising CASx edge to next cycle
′
s last rising CASx edge.
The last rising CASx edge to first falling CASx edge.
The first DQx controlled by the first CASx to go low.
The last DQx controlled by the last CASx to go high.
Each CASx must meet minimum pulse width.
The last falling CASx edge to the first rising CASx edge.
If
t
RASS
≥
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 1024(1K) cycles of burst refresh must be executed within
16ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
6.
5.
9.
8.
3.
2.
1.
4.
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15.
16.
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27.
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