參數(shù)資料
型號: KM432S2030B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512K x 32Bit x 4 Banks Synchronous DRAM(512K x 32位 x 4 組同步動態(tài)RAM)
中文描述: 為512k × 32Bit的× 4銀行同步DRAM(512k × 32的位× 4組同步動態(tài)RAM)的
文件頁數(shù): 2/9頁
文件大?。?/td> 68K
代理商: KM432S2030B
KM432S2030B
CMOS SDRAM
REV. 4 July 1998
Preliminary
The KM432S2030B is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
512K x 32Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
Part No.
Max Freq.
125MHz
100MHz
100MHz
Interface Package
KM432S2030BT-G/F8
KM432S2030BT-G/FL
KM432S2030BT-G/F10
LVTTL
86
TSOP (II)
FUNCTIONAL BLOCK DIAGRAM
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
512K x 32
512K x 32
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
512K x 32
512K x 32
Timing Register
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