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參數(shù)資料
| 型號(hào)： | KM432S2030B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 32Bit x 4 Banks Synchronous DRAM(512K x 32位 x 4 組同步動(dòng)態(tài)RAM) |
| 中文描述： | 為512k × 32Bit的× 4銀行同步DRAM（512k × 32的位× 4組同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | KM432S2030B |
KM432S2030B
CMOS SDRAM
REV. 4 July 1998
Preliminary
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-8
-L
-10
Unit
Note
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
CC
8
1000
10
1000
10
1000
ns
1
CAS latency=2
12
12
13
CLK to valid
output delay
CAS latency=3
t
SAC
6
6
7
ns
1,2
CAS latency=2
7
7
8
Output data
hold time
CAS latency=3
t
OH
3
3
3
ns
2
CAS latency=2
3
3
3
CLK high pulse width
t
CH
3
3
3.5
ns
3
CLK low pulse width
t
CL
3
3
3.5
ns
3
Input setup time
t
SS
2
2
2.5
ns
3
Input hold time
t
SH
1
1
1
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
6
6
7
ns
CAS latency=2
7
7
8
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. This parameter is guaranteed by design not by test.
Notes :
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