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參數(shù)資料
| 型號： | KM44L32031BT-G(L)0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 1.0 |
| 中文描述： | DDR SDRAM的規(guī)范版本1.0 |
| 文件頁數(shù)： | 22/53頁 |
| 文件大?。?/td> | 669K |
| 代理商： | KM44L32031BT-G(L)0 |
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REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
3.3.3 Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read command continues to appear on the outputs until the CAS latency from
the interrupting Read command is satisfied. At this point the data from the interrupting Read command
appears. Read to Read interval is minimum 1 Clock.
Command
< Burst Length=4, CAS Latency=2 >
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ
′
s
CAS Latency=2
D
out
A
0
D
out
A
1
D
out
B
0
D
out
B
1
D
out
B
2
D
out
B
3
2
0
1
5
3
4
8
6
7
CK
CK
3.3.4 Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data conten-
tion on the I/O bus by placing the DQ
’
s(Output drivers) in a high impedance state. To insure the DQ
’
s are tri-
stated one cycle before the beginning the write operation, Burst stop command must be applied at least 2
clock cycles for CL=2 and at least 3 clock cycles for CL=2.5 before the Write command.
Command
< Burst Length=4, CAS Latency=2 >
READ
Burst Stop
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
DQS
DQ
′
s
CAS Latency=2
Dout 0
Dout 1
Din 0
Din 1
Din 2
Din 3
2
0
1
5
3
4
8
6
7
CK
CK
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read
burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been
issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up
to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
Figure 11. Read interrupted by a read timing
Figure 12. Read interrupted by a write and burst stop timing.
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