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| 型號(hào)： | KM48S8020B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動(dòng)態(tài)RAM) |
| 中文描述： | 4米× 8位× 2銀行同步DRAM（4米× 8位× 2組同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 1/43頁(yè) |
| 文件大?。?/td> | 604K |
| 代理商： | KM48S8020B |
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KM48S8020B
CMOS SDRAM
REV .7 July 1998
Revision History
Revision .3(November 1997)
- t
RDL
has changed 10ns to 12ns.
- Binning -10 does not meet PC100 characteristics .
So AC parameter/Characteristics have changed to 64M 2nd values.
Revision .4 (February 1998)
- Input leakage Currents (Inputs / DQ) are changed.
IIL(Inputs) :
±
5uA to
±
1uA, I
IL
(DQ) :
±
5uA to
±
1.5uA.
- The measuring condition of tR/tF is clearly defined each as
0pF +50
to V
SS
/V
DD
, 50pF +50
to V
SS
/V
DD
- Cin to be measured at V
DD
= 3.3V, TA = 23
°
C, f = 1MHz, V
REF
=1.4V
±
200 mV.
- AC Operating Condition is changed as defined :
VIH(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
VIL(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
- ICC3PS is changed 1mA to 2mA.
- ICC6 for Low power is changed 400uA to 450uA.
Revision .5 (March 1998)
- I
CC2
N, I
CC2
NS, I
CC3
N & I
CC3
NS values are changed.
Revision .6 (June 1998)
- t
SH
(-10 binning) is revised.
Revision .7 (July 1998)
- Simplified Truth Table is revised.
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