參數(shù)資料
型號(hào)： KM44L32031BT-G(L)Y
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR SDRAM Specification Version 1.0
中文描述： DDR SDRAM的規(guī)范版本1.0
文件頁數(shù)： 42/53頁
文件大?。?/td> 669K
代理商： KM44L32031BT-G(L)Y
- 42 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
8Mx16
Table 12. 128Mb DDR SDRAM IDD SPEC Table
Symbol
K4H281638B-TCA2
(DDR266A)
typical
90
140
21
40
30
25
45
210
150
195
2
1
300
K4H281638B-TCB0
(DDR266B)
typical
90
140
21
40
30
25
45
210
150
195
2
1
300
K4H281638B-TCA0
(DDR200)
typical
80
135
20
35
27
20
35
155
110
180
2
1
275
Unit
Notes
worst
worst
worst
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
95
155
25
45
35
30
50
245
165
210
2
1
340
95
155
25
45
35
30
50
245
165
210
2
1
340
85
150
24
40
32
25
40
175
125
190
2
1
300
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD6
Normal
Low power
IDD7
Optional
< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
相關(guān)PDF資料
PDF描述
KM48S2020C 1M x 8Bit x 2 Banks Synchronous DRAM(1M x 8位 x 2組同步動(dòng)態(tài)RAM)
KM48S8020B 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動(dòng)態(tài)RAM)
KM48S8030D 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL
KM48S8030 2M x 8Bit x 4 Banks Synchronous DRAM
KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KM44L32031BT-GLZ/Y/0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR SDRAM Specification Version 1.0
KM44S16020CT-G10 制造商:SEC 功能描述:
KM44S32030 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 4Bit x 4 Banks Synchronous DRAM
KM44S32030B 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
KM44S32030BT-G/F10 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*