參數(shù)資料
型號: KMPC8533EVTAQG
廠商: Freescale Semiconductor
文件頁數(shù): 67/112頁
文件大小: 0K
描述: IC MPU POWERQUICC III 783-PBGA
標(biāo)準(zhǔn)包裝: 5
系列: MPC8xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
58
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 38 shows the PCI input AC timing conditions.
Figure 38. PCI Input AC Timing Measurement Conditions
Figure 39 shows the PCI output AC timing conditions.
Figure 39. PCI Output AC Timing Measurement Condition
16 High-Speed Serial Interfaces (HSSI)
The MPC8533E features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial
interconnect applications.Both SerDes1 and SerDes2 can be used for PCI Express data transfers
application.This section describes the common portion of SerDes DC electrical specifications, which is the
DC requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference
circuits are also shown.
16.1
Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 40 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for
description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a
receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B.
tPCIVKH
CLK
Input
tPCIXKH
CLK
Output Delay
tPCKHOV
High-Impedance
tPCKHOZ
Output
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