![](http://datasheet.mmic.net.cn/300000/KS16114_datasheet_16200449/KS16114_28.png)
KS16112/4
9600/14400 bps FAX MODEM
-
28
-
The modem will assert IRQ and set INTA 1 when BDA 1 is set by the modem if control bit INTE 1 is set
( interrupt enabled ). If INTE 1 is reset ( interrupt disabled ) IRQ and INTA 1 are unaffected by BDA 1.
The modem will assert IRQ and set INTA 2 when BDA 2 is set by the modem if control bit INTE 2 is set
( interrupt enabled ). If INTE 2 is reset ( interrupt disabled ) IRQ and INTA 2 are unaffected by BDA 2.
INTE 1
INTE 2
Interrupt Enable 1
Interrupt Enable 2
1E : 2 ( 0 )
1E : 5 ( 0 )
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
01
11
02
12
03
13
04
14
05
15
06
16
07
17
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
18
09
19
0A
1A
0B
1B
0C
1C
0D
1D
0E
1E
0F
1F
Host Register
( Hex )
INTADR
( Hex )
Host Register
( Hex )
INTADR
( Hex )
When control bit INTML is set when programmable interrupts are enabled ( PINTE is set ), the
modem will logically AND the contents of the interface memory register specified by INTADR with the
contents of INTMSK. Thus, the IRQ condition will be met if all the bits in the specified register masked by
INTMSK are set. When control bit INTML is reset when programmable interrupts are enabled
( PINTE is set ), the modem will logically OR the contents of the interface memory register specified by
INTADR with the contents of INTMSK. Thus, the IRQ condition will be met if any the bits in the specified
register masked by INTMSK are set. Note that ITRIG places additional interrupt triggering requirements on
the programmable interrupt which must also be met in order for IRQ to be asserted by the modem.
INTML
Interrupt Mask Logic (AND / OR Logic)
0A : 5 ( 0 )