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參數(shù)資料
| 型號： | KS16114 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 9600/14400 bps FAX MODEM |
| 中文描述： | 14400分之9600基點傳真調制解調器 |
| 文件頁數(shù)： | 38/69頁 |
| 文件大?。?/td> | 513K |
| 代理商： | KS16114 |
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KS16112/4
9600/14400 bps FAX MODEM
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Set WT1 and/or WT2 to instruct the modem that a RAM write operation will take place when RA1 and/or
RA2 is set.
Write the desired data into the interface memory RAM data registers YDL1 and YDM1 and/or YDL2
and YDM2.
Set RA1 and/or RA2 to instruct the modem to perform the RAM write operation.
BDA1 and/or BDA2 will be set when the transfer from the interface memory RAM data registers into
RAM has been completed.
When BDA1 and/or BDA2 is set, IRQ is also asserted if INTE1 and/or INTE2 is set.
Reset INTA1 and BDA1 and/or INTA2 and BDA2 by reading or writing to YDL1 and/or YDL2. Reading or
writing YDL1 and/or YDL2 also causes IRQ to return to the inactive state if no other interrupts are pending.
4 Parallel Data Transfers
Parallel data transfers use register 10h in the interface memory ( DBFR ). The modem and the host can
synchronize data transfers by observing the BDA2 bit in the interface memory. Parallel data transfers may
also be performed under IRQ interrupts ( see INTE2 and INTA2 bit descriptions ).
4.1 Receiving Parallel Data
During parallel data mode ( PDME is set ), the modem writes received data to DBFR once every eight bit
times. When received data is available the modem sets the BDA2 bit. The BDA2 bit is automatically reset
when the host reads DBFR. When BDA2 is set the host must take action within eight bit times or the data
will be lost since the modem will overwrite DBFR ( DBFR overrun condition ).
During parallel data mode ( PDME is set ), the modem reads DBFR once every eight bit times. The BDA2
bit is set by the modem when DBFR has been read, thus requesting the next transmit data byte. The BDA2
bit is reset automatically when the host writes to DBFR. When BDA2 is set the modem must respond within
eight bit times or the modem will retransmit the data in register DBFR ( DBFR underrun condition ).
The LSB ( bit 0 ) in DBFR is transmitted first in time and the MSB ( bit 7 ) is transmitted last.
The least significant bit of register DBFR represents the oldest data and the most significant bit represents
the newest data received.
4.2 Transmitting Parallel Data
相關PDF資料 |
PDF描述 |
|---|---|
| KS16112 | CAP 33PF 50V 5% NPO(C0G) SMD-0603 TR-7-PA |
| KS16116-02 | 9600 bps FAX MODEM(9600bps傳真調制解調器) |
| KS16117-02 | 14400 bps FAX MODEM(14400bps傳真調制解調器) |
| KS16118 | 9600bps FAX super one-chip(9600bps傳真調制解調器) |
| KS16120B | DSP for Digital Answering Phone(用于數(shù)字應答電話的DSP) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| KS16-14 | 制造商:MAJOR 功能描述: |
| KS-16287L1 | 制造商:WSTELC 功能描述: |
| KS-16287L2 | 制造商:WSTELC 功能描述: |
| KS16390 | 制造商: 功能描述: 制造商:Cornell Dubilier Electronics 功能描述: 制造商:undefined 功能描述: |
| KS16479 | 制造商:Olympic Controls Corporation 功能描述: |
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