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參數(shù)資料
| 型號： | KS57C2504 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機的小型通用紅外遙控器 |
| 文件頁數(shù)： | 23/94頁 |
| 文件大小： | 763K |
| 代理商： | KS57C2504 |
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S3C7254
PRODUCT SPECIFICATION
4–23
CLOCK OUTPUT MODE REGISTER (CLMOD)
The clock output mode register, CLMOD, is a 4-bit
register that is used to enable or disable clock
output to the CLO pin and to select the CPU clock
source and frequency. CLMOD is addressable by 4-
bit write instructions only.
RESET
clears CLMOD to logic zero, which
automatically selects the CPU clock as the clock
source (without initiating clock oscillation), and
disables clock output.
CLMOD.3 is the enable/disable clock output control
bit; CLMOD.1 and CLMOD.0 are used to select one
of four possible clock sources and frequencies:
normal CPU clock, fxx/8, fxx/16, or fxx/64. Table 6–
5. Clock Output Mode Register (CLMOD)
Organization
Table 8. Clock Output Mode Register (CLMOD) Organization
CLMOD Bit Settings
CLMOD.1
0
Resulting Clock Output
CLMOD.0
0
Clock Source
Frequency
CPU clock (fx/4, fx/8, fx/64, fxt/4)
1.05 MHz, 524 kHz, 65.5 kHz,
8.19 kHz
524 kHz, 4.096 kHz
262 kHz, 2.048 kHz
65.5 kHz, 0.512 kHz
0
1
1
1
0
1
fxx/8
fxx/16
fxx/64
CLMOD.3
0
1
Result of CLMOD.3 Setting
Clock output is disabled
Clock output is enabled
NOTE
:
Frequencies assume that fxx is 4.19 MHz and fxt is 32.768 kHz.
PM4.0
P4.0 OUTPUT LATCH
CLO
CLMOD.3
CLMOD.2
CLMOD.1
CLMOD.0
CLOCK
SELECTOR
CLOCKS
4
(fxx/8, fxx/16, fxx/64, CPU clock)
Figure 22. CLO Output Pin Circuit Diagram
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