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參數(shù)資料
| 型號： | KS57C2504 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機的小型通用紅外遙控器 |
| 文件頁數(shù)： | 26/94頁 |
| 文件大小： | 763K |
| 代理商： | KS57C2504 |
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PRODUCT SPECIFICATION
S3C7254
4–26
Table 9. Interrupt Request Flag Conditions and Priorities
Interrupt
Source
INTB
Internal /
External
I
Pre-condition for IRQx Flag Setting
Interrupt
Priority
1
IRQ Flag
Name
IRQB
Reference time interval signal from basic
timer
Both rising and falling edges detected at INT4
Rising or falling edge detected at INT0 pin
Rising or falling edge detected at INT1 pin
Completion signal for serial transmit-and-re-
ceive or receive-only operation
Signals for TCNT0 and TREF0 registers
match
When a rising or falling edge detected at any
one of the K0–K3 pins
Rising or falling edge detected at INT2
INT4
INT0
INT1
INTS
E
E
E
I
1
2
3
4
IRQ4
IRQ0
IRQ1
IRQS
INTT0
I
5
IRQT0
INTK
E
6
IRQK
INT2
*
INTW
E
—
IRQ2
I
Time interval of 0.5 second or 3.19 ms
—
IRQW
NOTE
:
The quasi-interrupt INT2 is only used for testing incoming signals.
INTERRUPT ENABLE FLAGS (IEX)
IEx flags, when set to logical one, enable specific
interrupt requests to be serviced. When the interrupt
request flag is set to logical one, an interrupt will not
be serviced until its corresponding IEx flag is also
enabled.
Interrupt enable flags can be read, written, or tested
directly by 1-bit instructions. IEx flags can be
addressed directly at their specific RAM addresses,
despite the current value of the enable memory
bank (EMB) flag.
Table 10. Interrupt Enable and Request Flag
Address
FB8H
FBAH
FBBH
FBCH
FBDH
FBEH
FBFH
Bit 3
IE4
0
0
0
0
IE1
0
Bit 2
IRQ4
0
0
0
0
IRQ1
0
Bit 1
IEB
IEW
IEK
IET0
IES
IE0
IE2
Bit 0
IRQB
IRQW
IRQK
IRQT0
IRQS
IRQ0
IRQ2
NOTES:
1.
2.
IEx refers generically to all interrupt enable flags.
IRQx refers generically to all interrupt request flags.
3.
4.
IEx = 0 is interrupt disable mode.
IEx = 1 is interrupt enable mode.
INTERRUPT PRIORITY REGISTER (IPR)
The 4-bit interrupt priority register (IPR) is used to
control multi-level interrupt handling. Its reset value
is logic zero. Before the IPR can be modified by 4-
bit write instructions, all interrupts must first be
disabled by a DI instruction.
By manipulating the IPR settings, you can choose to
process all interrupt requests with the same priority
level, or you can select one type of interrupt for
high-priority processing. A low-priority interrupt can
itself be interrupted by a high-priority interrupt, but
not by another low-priority interrupt. A high-priority
interrupt cannot be interrupted by any other interrupt
source.
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