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參數(shù)資料
| 型號： | KS57C2504 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機的小型通用紅外遙控器 |
| 文件頁數(shù)： | 69/94頁 |
| 文件大?。?/td> | 763K |
| 代理商： | KS57C2504 |
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S3C7254
PRODUCT SPECIFICATION
4–69
SERIAL I/O MODE REGISTER (SMOD)
The serial I/O mode register, SMOD, is an 8-bit
register that specifies the operation mode of the
serial interface. Its reset value is logical zero.
SMOD is organized in two 4-bit registers, as follows:
SMOD register settings enable you to select either
MSB-first or LSB-first serial transmission, and to
operate in transmit-and-receive mode or receive-
only mode. SMOD is a write-only register and can
be addressed only by 8-bit RAM control instructions.
One exception to this is SMOD.3, which can be
written by a 1-bit RAM control instruction. When
SMOD.3 is set to 1, the contents of the serial
interface interrupt request flag, IRQS, and the 3-bit
serial clock counter are cleared, and SIO operations
are initiated. When the SIO transmission starts,
SMOD.3 is cleared to logical zero.
Table 29. SIO Mode Register (SMOD) Organization
SMOD.0
0
1
0
1
0
Most significant bit (MSB) is transmitted first
Least significant bit (LSB) is transmitted first
Receive-only mode
Transmit-and-receive mode
Disable the data shifter and clock counter; retain contents of IRQS flag when serial
transmission is halted
Enable the data shifter and clock counter; set IRQS flag to "1" when serial
transmission is halted
Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset
this bit to logic zero
Bit not used; value is always "0"
SMOD.1
SMOD.2
1
SMOD.3
1
SMOD.4
0
SMOD.7
0
SMOD.6
0
SMOD.5
0
Clock Selection
R/W Status of SBUF
SBUF is enabled when SIO
operation is halted or when
SCK
goes high.
External clock at
SCK
pin
0
0
1
0
1
0
1
x
0
Use TOL0 clock from TC0
CPU clock: fxx/4, fxx/8, fxx/64
4.09 kHz clock: fxx/2
10
Enable SBUF read/write
SBUF is enabled when SIO
operation is halted or when
SCK
goes high.
1
1
1
262 kHz clock: fxx/2
4
NOTES
:
1.
2.
3.
'fxx' = system clock; 'x' means 'don't care.'
kHz frequency ratings assume a system clock (fxx) running at 4.19 MHz.
The SIO clock selector circuit cannot select a fxx/2
4
clock if the CPU clock is fxx/64
.
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