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參數(shù)資料
| 型號： | KS57C2504 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 4位微控制器 |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 4位單片機的小型通用紅外遙控器 |
| 文件頁數(shù)： | 37/94頁 |
| 文件大小： | 763K |
| 代理商： | KS57C2504 |
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S3C7254
PRODUCT SPECIFICATION
4–37
PORT 1 MODE REGISTER (P1MOD)
P1MOD register settings determine if port 1 is used
for digital input or for analog input. The P1MOD
register is a 4-bit write only register. P1MOD is
mapped to address FE2H. A reset operation
initializes all P1MOD values to logic zero,
configuring port 1 as an analog input port.
When a P1MOD bit is "0", the corresponding pin
is configured as a analog input pin. When set to
"1", it is configured as an digital input pin:
P1MOD.0 corresponds to P1.0, and P1MOD.1
to P1.1.
NOTE
INT0 and INT1 can occur only when the port
is configured to digital input. If you change
the input mode from digital to analog using
P1MOD settings, IRQ0 and IRQ1 will be set.
When you use analog input, you must
clear the corresponding interrupt enable
flag (IEx).
That is, clear IE0 when P1.0 is
an analog input and clear IE1 when P1.1 is
an analog input.
PULL-UP RESISTOR MODE REGISTER (PUMOD)
The pull-up resistor mode registers (PUMOD1 and
PUMOD2) are used to assign internal pull-up
resistors by software to specific ports. When a
configurable I/O port pin is used as an output pin, its
assigned pull-up resistor is automatically disabled,
even though the pin's pull-up is enabled by a
corresponding PUMOD bit setting.
Table 19. Pull-Up Resistor Mode Register (PUMOD) Organization
PUMOD ID
PUMOD1
Address
FDCH
FDDH
FDEH
Bit 3
PUR3
0
PUR1.3
Bit 2
PUR2
0
PUR1.2
Bit 1
“0”
0
PUR1.1
Bit 0
PUR0
PUR4
PUR1.0
PUMOD2
NOTE:
When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2,
and so on.
PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors
P6 and P7 enable pull-up resistors.
BITS
SMB
LD
LD
EMB
15
EA,#0CH
PUMOD1,EA
;
P2 and P3 enable
N-CHANNEL OPEN-DRAIN MODE REGISTER
The n-channel open-drain mode register (PNE) is
used to configure ports 0, 2, 3 and 4 to n-channel
open-drain or as push-pull outputs. When a bit in the
PNE register is set to "1", the corresponding output
pin is configured to n-channel, open-drain; when set
to "0", the output pin is configured to push-pull. The
PNE register consists of an 8-bit register and a 4-bit
register; PNE1 and PNE3 can be addressed by 4-bit
write instructions only and PNE2 by 8-bit write
instructions only.
PNE ID
PNE1
PNE2
ADDRESS
FA6H
FA8H
FA9H
FAAH
Bit 3
P0.3
P2.3
P3.3
0
Bit 2
P0.2
P2.2
P3.2
P4.2
Bit 1
P0.1
P2.1
P3.1
P4.1
Bit 0
P0.0
P2.0
P3.0
P4.0
PNE3
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