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參數(shù)資料
| 型號： | KS9284 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor(數(shù)字信號處理器) |
| 中文描述： | 數(shù)字信號處理器（數(shù)字信號處理器） |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 112K |
| 代理商： | KS9284 |
KS9284
DIGITAL SIGNAL PROCESSOR
1) CNTL-Z Register
It is a register to control zero cross mute of audio data, phase terminal control, phase servo and having or not CRCF data
in SQDT.
Table 2.
2) CNTL-S Register
It is a register to control frame sync protection and attenuation
Table 3.
3) CNTL-L, U Register
After the number of track that must be counted is inputted from micom , the data is loaded to tracking counter by CNTL-L,
U register.
4) CNTL-W Register
It is a register to control CLV-servo.
Table 4.
DATA
DATA = 0
DATA = 1
ZCMT
HIPD
NCLV
CRCQ
D3
D2
D1
D0
Zero cross mute is OFF
It operates phase normally
Phase servo is acted by frame sync
SQDT output except for SQOK
Zero cross mute is ON
The phase becomes “L” to “Hi-Z”
Phase servo is controlled by base counter
SQDT = CRCF when S0S1 = “H”
FSEM
FSEL
FRAME
0
0
1
1
0
1
0
1
2
4
8
13
WSEL
CLOCK
0
1
±
3
±
7
ATTM
MUTE
dB
0
0
1
1
0
1
0
1
0
-
∞
-12
-12
DATA
DATA = 0
DATA = 1
Comment
COM
WB
WP
GAIN
D3
D2
D1
D0
XTFR/4 and PBFR/4
XTFR/32
XTFR/4
-12dB
Phase comparison frequency control during Phase - mode
Bottom hold period control during speed or H.Speed-mode.
Peak hold period control during Speed-mode
SMDP gain control during Speed or H.Speed-Mode
XTFR/16
XTFR/2
0dB
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