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參數(shù)資料
| 型號： | KS9284 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor(數(shù)字信號處理器) |
| 中文描述： | 數(shù)字信號處理器（數(shù)字信號處理器） |
| 文件頁數(shù)： | 5/25頁 |
| 文件大小： | 112K |
| 代理商： | KS9284 |
KS9284
DIGITAL SIGNAL PROCESSOR
PIN DESCRIPTION
(continued)
Pin No.
Symbol
I/O
Description
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SQOK
SBCK
SBDT
DV
DD
1
MUTE
MLT
MDAT
MCK
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
FLAG1
FLAG2
FLAG3
FLAG4
O
I
O
-
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
The CRC check result signal output of subcode-Q
Subcode data bit clock
Subcode serial data output
Digital supply voltage 1
Mute control input (“H”: Mute ON)
Latch signal input from micom
Serial data input from micom
Serial data transfering clock input from micom
Data port 7 for external SRAM (MSB)
Data port 6 for external SRAM
Data port 5 for external SRAM
Data port 4 for external SRAM
Data port 3 for external SRAM
Data port 2 for external SRAM
Data port 1 for external SRAM
Data port 0 for external SRAM (LSB)
Monitoring output for C1 error correction (RA0)
Monitoring output for C1 error correction (RA1)
Monitoring output for C2 error correction (RA2)
Monitoring output for C2 error correction (RA3)
C2 decoder flag (“H”: when the processing C2 code is impossible correction
status /RA4)
VCOI/2 clock (4.3218/8.6436MHz) ; when locked in with EFMI (RA5)
Digital ground 2
Unprotected frame sync (RA6)
Frame sync protection status (RA7)
RAM overflow and underflow status (RA8)
4.2336MHz clock output (RA9)
16.9344MHz clock output (RA10)
Write enable output to external SRAM
Chip select output to external SRAM
51
FLAG5
I/O
52
53
54
55
56
57
58
59
60
/PBCK
DV
SS
2
FSDW
ULKFS
/JIT
C4M
C16M
/WE
/ CS
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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