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參數(shù)資料
| 型號(hào)： | KS9284 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processor(數(shù)字信號(hào)處理器) |
| 中文描述： | 數(shù)字信號(hào)處理器（數(shù)字信號(hào)處理器） |
| 文件頁數(shù)： | 4/25頁 |
| 文件大小： | 112K |
| 代理商： | KS9284 |
KS9284
DIGITAL SIGNAL PROCESSOR
PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
AV
DD
1
DPDO
DPFIN
DPFOUT
CNTVOL
AV
SS
1
DATX
XIN
XOUT
WDCH1
LRCH1
SADT1
DV
SS1
BCK1
C2PO
TIM2
/BCK1
/BCK2
BCK2
LRCH2
SADT2
TEST0
WDCH2
EMPH
LKFS
S0S1
RESET
SQEN
SQCK
SQDT
-
Analog supply voltage 1
Charge pump output for master PLL
Filter input for master PLL
Filter output for master PLL
VCO control voltage for master PLL
Analog ground 1
Digital audio output
X-tal oscillator input (16.9344MHz / 33.8688MHz)
X-tal oscillator output
Word clock of 48 bits/slot
Channel clock of 48 bits/slot
Serial audio data output with 48 bits/slot
Digital ground 1
Serial audio data bit clock for 48 bits/slot
C2 pointer for serial audio data
Normal or double speed control output pin
Inverted clock of BCK1
Inverted clock of BCK2
Serial audio data bit clock for 64 bits/slot
Channel clock for 64 bits/slot
Serial audio data output with 64 bits/slot
Test input pin (“L”: normal, “H”: test)
Word clock of 64 bit/slot
Emphasis/Non-emphasis output (“H” : Emphasis)
The lock status output of frame sync
Output of subcode sync signal (S0 + S1)
System reset at “L”
SQCK control input (“L”: internal clock, “H”: external clock)
Subcode-Q data bit clock
Subcode-Q data serial output
O
I
O
I
-
O
I
O
O
O
O
-
O
O
O
O
O
O
O
O
I
O
O
O
O
I
I
I/O
O
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| KS9286B-L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR for CDP |
| KS9287 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DIGITAL SIGNAL PROCESSOR |
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