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參數(shù)資料
| 型號： | KS9284 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor(數(shù)字信號處理器) |
| 中文描述： | 數(shù)字信號處理器（數(shù)字信號處理器） |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 112K |
| 代理商： | KS9284 |
KS9284
DIGITAL SIGNAL PROCESSOR
PIN DESCRIPTION
(continued)
(NOTE)
1. PBFR: 7.35KHz Write frame clock produced by data which being reproduced.
2. /PBCK : Channel bit clock of data which being reproduced.
3. /JIT : Display signal of either RAM overflow or underflow for
±
4 frame jitter margin.
Pin No.
Symbol
I/O
Description
61
62
63
64
65
66
67
68
69
SEL1
SEL2
SEL3
SEL4
TEST1
EFMI
APDO1
/ISTAT
TRCNT
I
I
I
I
I
I
X-tal selection terminal (“L”:16.9344MHz; “H” : 33.8688MHz)
DPLL selection terminal (“L”: DPLL, “H” : APLL)
CD-ROM selection terminal (“L”: CDP, “H” : CD-ROM)
SRAM selection terminal (“L”: internal SRAM, “H” : external SRAM)
Test terminal (“L”: normal, “H”: test)
EFM data input
Charge pump output for analog PLL
The internal status output
Tracking clock input signal
Output signal of LKFS conditions sampled PBFR/16
(If LKFS is “H”, lock is “H”. If the LKFS is sampled “L” at least 8 times by PBFR/16,
lock is “L”)
Write frame clock (Lock : 7.35KHz)
LPF time constant control of the spindle servo error signal
ON/OFF control signal for spindle servo
Digital supply vlotage 2
Spindle motor driving output (rough control in the speed mode, phase control in
the phase mode
Spindle motor (Velocity control in the phase mode)
VCO output
VCO inut (when the state is lock by means of PBFR, it is 8.6436MHz)
Double speed mode control (“H”: normal speed, “L”: 2-times speed )
Analog PLL charge pump output for double speed mode
O
O
I
70
LOCK
O
71
72
73
74
PBFR
SMEF
SMON
DV
DD
2
O
O
O
-
75
SMDP
O
76
77
SMSD
VCOO
O
O
78
79
80
VCOI
DSPEED
APDO2
I
I
O
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